- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358818 > LM2502 (National Semiconductor Corporation) Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer PDF資料下載
參數(shù)資料
| 型號(hào)： | LM2502 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| 中文描述： | 移動(dòng)像素鏈路（MPL）的顯示接口串行器和解串 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大小： | 1089K |
| 代理商： | LM2502 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁
Application Information
(Continued)
DISPLAY APPLICATION
The LM2502 chipset is intended for Interface between a host
(processor) and a Display. It supports a 16 or 8-bit CPU style
interface and can be configured for i80 or m68 modes.
The Master side connection is shown in
Figure 19
. Input
Clock frequency and the selection of the PLL_CON setting
are determined by system parameters. These include the
required display bandwidth, the Master load rate and the
Display Driver input timing requirements. See the
System
Considerations
section for more details.
The Display side parallel bus may be connected to one or
two displays. Each display has its own chipselect signal. If
only one display is required, the unused CS signal should be
tied HIGH (V
) on the Master, and the unused output left
open on the Slave. The Slave provides an optional clock
output. If this is desired the CLKDIS
*
pin needs to be also
tied HIGH. A different PLL_CON setting can be used to alter
the frequency if desired. As the Divisor setting in the Slave is
not used for data recovery. For the dual display application,
the multidrop bus should be laid out to minimize any result-
ing stub lengths on the Data, A/D, and control signals.
If required, the Slave output clock can be enabled to provide
a output frequency reference. The frequency can be ad-
justed by setting different PLL_CON (divisor) settings (on the
Slave). This can then be used as a frequency reference
signal to the display module or other subsystem (ie camera
module). If the CLK output is not needed, tie the Slave
CLKDIS
*
pin Low to disable it. The Clock is available when
ever the MPL link is enabled.
20093321
FIGURE 18. LM2502 UFBGA Package PWR (V
DD
) and GND (V
SS
) Balls
L
www.national.com
23
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LM2502SM | Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| LM2502SQ | Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| LM251 | CYAN LAMP LED |
| LM2567 | LAN DC/DC Converter |
| LM2567M | LAN DC/DC Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM2502SM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| LM2502SM/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| LM2502SMX/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| LM2502SQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| LM2502SQ/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。