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參數(shù)資料
| 型號： | LM2324 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum⑩ 2.0 GHz Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLLatinum⑩射頻個(gè)人通訊2.0 GHz的頻率合成器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 157K |
| 代理商： | LM2324 |
2.0 Programming Description
(Continued)
2.3 N REGISTER
If the address bit is LOW (ADDR=0) when LE is transitioned high, data is transferred from the 18-bit shift register into the 17-bit
N register. The N register consists of the 5-bit swallow counter (A counter), the 10-bit programmable counter (B counter) and the
control word. Serial data format is shown below in tables 2.3.1 and 2.3.2. The pulse swallow function which determines the divide
ratio is described in section 2.3.3. Data is clocked into the shift register MSB first.
MSB
17
SHIFT REGISTER BIT LOCATION
11
10
9
Data Field
LSB
16
15
14
13
12
8
7
6
5
4
3
2
1
0
Register
ADDR Field
N
NB_CNTR[9:0]
N12
NA_CNTR[4:0]
N5
N4
CTL_WORD[1:0]
N1
0
N16
N15
N14
N13
N11
N10
N9
N8
N7
N6
N3
N2
N0
2.3.1 5-Bit Swallow Counter Divide Ratio (A Counter)
Swallow Count
(A)
0
1
31
NA_CNTR[4:0]
N4
0
0
1
N6
0
0
1
N5
0
0
1
N3
0
0
1
N2
0
1
1
Notes:
Swallow Counter Value: 0 to 31
NB_CNTR
≥
NA_CNTR
2.3.2 10-Bit Programmable Counter Divide Ratio (B Counter)
NB_CNTR[10:0]
N13
0
0
1
Divide Ratio
3
4
1023
N16
0
0
1
N15
0
0
1
N14
0
0
1
N12
0
0
1
N11
0
0
1
N10
0
0
1
N9
0
1
1
N8
1
0
1
N7
1
0
1
Notes:
Divide ratio: 3 to 1,023 (Divide ratios less than 3 are prohibited)
NB_CNTR
≥
NA_CNTR
2.3.3 Pulse Swallow Function
The N divider counts such that it divides the VCO RF frequency by (P+1)Atimes, and then divides by P (B -A) times. The B value
(NB_CNTR) must be
≥
3. The continuous divider ratio is from 992 to 32,767. Divider ratios less than 992 are achievable as long
as the binary counter value is greater than the swallow counter value (NB_CNTR
≥
NA_CNTR).
f
VCO
= N x (f
OSC
/R)
N = (P x B) + A
f
VCO
:
Output frequency of external voltage controlled oscillator (VCO)
f
OSC
:
Output frequency of the external reference frequency oscillator
R:
Preset divide ratio of binary 10-bit programmable reference counter (2 to 1023)
N:
Preset divide ratio of main 15-bit programmable integer N counter (992 to 32,767)
B:
Preset divide ratio of binary 10-bit programmable B counter (3 to 1023)
A:
Preset value of binary 5-bit swallow A counter (0
≤
A
≤
31, A
≤
B)
P:
Preset modulus of dual modulus prescaler (P=32)
2.3.4 CTL_WORD
MSB
LSB
N1
N0
CNT_RST
PWDN
L
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