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參數(shù)資料
| 型號： | LM2324 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum⑩ 2.0 GHz Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLLatinum⑩射頻個人通訊2.0 GHz的頻率合成器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 157K |
| 代理商： | LM2324 |
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The LMX2324 register set can be accessed through the MICROWIRE interface. A 18-bit shift register is used as a temporary reg-
ister to indirectly program the on-chip registers. The shift register consists of a 17-bit DATA[16:0] field and a 1-bit address (ADDR)
field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift register in
the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Load Enable (LE) signal, data stored
in the shift register is loaded into the addressed latch.
MSB
LSB
DATA[16:0]
ADDR
0
17
1
2.1.1 Registers’ Address Map
When Load Enable (LE) is transitioned high, data is transferred from the 18-bit shift register into the appropriate latch depending
on the state of the ADDRESS bit. A multiplexing circuit decodes the address bit and writes the data field to the corresponding in-
ternal register.
REGISTER
ADDRESSED
R Register
N Register
ADDRESS BIT
ADDR
1
0
L
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