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參數(shù)資料
| 型號： | LM12H458MWG-MCP |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CDFP44 |
| 文件頁數(shù)： | 24/43頁 |
| 文件大小： | 991K |
| 代理商： | LM12H458MWG-MCP |
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4.0 Sequencer
The Sequencer uses a 3-bit counter (Instruction Pointer, or
IP, in
Figure 9) to retrieve the programmable conversion in-
structions stored in the Instruction RAM. The 3-bit counter is
reset to 000 during chip reset or if the current executed in-
struction has its Loop bit (Bit 1 in any Instruction RAM “00”)
set high (“1”). It increments at the end of the currently ex-
ecuted instruction and points to the next instruction. It will
continue to increment up to 111 unless an instruction’s Loop
bit is set. If this bit is set, the counter resets to “000” and ex-
ecution begins again with the first instruction. If all instruc-
tions have their Loop bit reset to “0”, the Sequencer will ex-
ecute all eight instructions continuously. Therefore, it is
important to realize that if less than eight instructions are
programmed, the Loop bit on the last instruction must be set.
Leaving this bit reset to “0” allows the Sequencer to execute
“unprogrammed” instructions, the results of which may be
unpredictable.
The Sequencer’s Instruction Pointer value is readable at any
time and is found in the Status register at Bits 8–10. The Se-
quencer can go through eight states during instruction ex-
ecution:
State 0: The current instruction’s first 16 bits are read from
the Instruction RAM “00”. This state is one clock cycle long.
State 1: Checks the state of the Calibration and Start bits.
This is the “rest” state whenever the Sequencer is stopped
using the reset, a Pause command, or the Start bit is reset
low (“0”). When the Start bit is set to a “1”, this state is one
clock cycle long.
State 2: Perform calibration. If bit 2 or bit 6 of the Configu-
ration register is set to a “1”, state 2 is 76 clock cycles long.
If the Configuration register’s bit 3 is set to a “1”, state 2 is
4944 clock cycles long.
State 3: Run the internal 16-bit Timer. The number of
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below
32T + 2
where 0
≤ T ≤ 216 1.
State 7: Run the acquisition delay and read Limit #1’s
value if needed. The number of clock cycles for 12-bit + sign
mode varies according to
9+2D
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0
≤ D ≤ 15.
The number of clock cycles for 8-bit + sign or “watchdog”
mode varies according to
2+2D
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0
≤ D ≤ 15.
State 6: Perform first comparison. This state is 5 clock
cycles long.
State 4: Read Limit #2. This state is 1 clock cycle long.
State 5: Perform a conversion or second comparison. This
state takes 44 clock cycles when using the 12-bit + sign
mode or 21 clock cycles when using the 8-bit + sign mode.
The “watchdog” mode takes 5 clock cycles.
www.national.com
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