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2.0 Internal User-Programmable
Registers (Continued)
Bits 12–15 are used to store the user-programmable acqui-
sition time. The Sequencer keeps the internal S/H in the ac-
quisition mode for a fixed number of clock cycles (nine clock
cycles, for 12-bit + sign conversions and two clock cycles for
8-bit + sign conversions or “watchdog” comparisons) plus a
variable number of clock cycles equal to twice the value
stored in Bits 12–15. Thus, the S/H’s acquisition time is (9 +
2D) clock cycles for 12-bit + sign conversions and (2 + 2D)
clock cycles for 8-bit + sign conversions or “watchdog” com-
parisons, where D is the value stored in Bits 12–15. The
minimum acquisition time compensates for the typical inter-
nal multiplexer series resistance of 2 k
, and any additional
delay created by Bits 12–15 compensates for source resis-
tances greater than 60
(100). (For this acquisition time
discussion, numbers in ( ) are shown for the LM12(H)454/8
operating at 5 MHz.) The necessary acquisition time is deter-
mined by the source impedance at the multiplexer input. If
the source resistance (R
S) < 60 (100) and the clock fre-
quency is 8 MHz, the value stored in bits 12–15 (D) can be
0000. If R
S > 60 (100), the following equations determine
the value that should be stored in bits 12–15.
D = 0.45 x R
S xfCLK
for 12-bits + sign
D = 0.36 x R
S xfCLK
for 8-bits + sign and “watchdog”
R
S is in k and fCLK is in MHz. Round the result to the next
higher integer value. If D is greater than 15, it is advisable to
lower the source impedance by using an analog buffer be-
tween the signal source and the LM12(H)458’s multiplexer
inputs. The value of D can also be used to compensate for
the settling or response time of external processing circuits
connected between the LM12454’s MUXOUT and S/H IN
pins.
Instruction RAM “01”
The second Instruction RAM section is selected by placing a
“01” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #1. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12(H)454/8 performs a
“watchdog” comparison of the sampled analog input signal
with the limit #1 value first, followed by a comparison of the
same sampled analog input signal with the value found in
limit #2 (Instruction RAM “10”).
Bit 8 holds limit #1’s sign.
Bit 9’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #1 to generate an interrupt, while a “0” causes a voltage
less than limit #1 to generate an interrupt.
Bits 10–15 are not used.
Instruction RAM “10”
The third Instruction RAM section is selected by placing a
“10” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #2. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12(H)454/8 performs a
“watchdog” comparison of the sampled analog input signal
with the limit #1 value first (Instruction RAM “01”), followed
by a comparison of the same sampled analog input signal
with the value found in limit #2.
Bit 8 holds limit #2’s sign.
Bit 9 ’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #2 to generate an interrupt, while a “0” causes a voltage
less than limit #2 to generate an interrupt.
Bits 10–15 are not used.
2.2 CONFIGURATION REGISTER
The Configuration register, 1000 (A4–A1, BW = 0) or 1000x
(A4–A0, BW = 1) is a 16-bit control register with read/write
capability. It acts as the LM12454’s and LM12(H)458’s “con-
trol panel” holding global information as well as start/stop, re-
set, self-calibration, and stand-by commands.
Bit 0 is the START/STOP bit. Reading Bit 0 returns an indi-
cation of the Sequencer’s status. A “0” indicates that the Se-
quencer is stopped and waiting to execute the next instruc-
tion. A “1” shows that the Sequencer is running. Writing a “0”
halts the Sequencer when the current instruction has fin-
ished execution. The next instruction to be executed is
pointed to by the instruction pointer found in the status reg-
ister. A “1” restarts the Sequencer with the instruction cur-
rently pointed to by the instruction pointer. (See Bits 8–10 in
the Interrupt Status register.)
Bit 1 is the LM12(H)454/8’s system RESET bit. Writing a “1”
to Bit 1 stops the Sequencer (resetting the Configuration reg-
ister’s START/STOP bit), resets the Instruction pointer to
“000” (found in the Interrupt Status register), clears the Con-
version FIFO, and resets all interrupt flags. The RESET bit
will return to “0” after two clock cycles unless it is forced high
by writing a “1” into the Configuration register’s Standby bit.
A reset signal is internally generated when power is first ap-
plied to the part. No operation should be started until the RE-
SET bit is “0”.
Writing a “1” to Bit 2 initiates an auto-zero offset voltage cali-
bration. Unlike the eight-sample auto-zero calibration per-
formed during the full calibration procedure, Bit 2 initiates a
“short” auto-zero by sampling the offset once and creating a
correction coefficient (full calibration averages eight samples
of the converter offset voltage when creating a correction co-
efficient). If the Sequencer is running when Bit 2 is set to “1”,
an auto-zero starts immediately after the conclusion of the
currently running instruction. Bit 2 is reset automatically to a
“0” and an interrupt flag (Bit 3, in the Interrupt Status register)
is set at the end of the auto-zero (76 clock cycles). After
completion of an auto-zero calibration, the Sequencer
fetches the next instruction as pointed to by the Instruction
RAM’s pointer and resumes execution. If the Sequencer is
stopped, an auto-zero is performed immediately at the time
requested.
Writing a “1” to Bit 3 initiates a complete calibration process
that includes a “l(fā)ong” auto-zero offset voltage correction (this
calibration averages eight samples of the comparator offset
voltage when creating a correction coefficient) followed by
an ADC linearity calibration. This complete calibration is
started after the currently running instruction is completed if
the Sequencer is running when Bit 3 is set to “1”. Bit 3 is re-
set automatically to a “0” and an interrupt flag (Bit 4, in the In-
terrupt Status register) will be generated at the end of the
calibration procedure (4944 clock cycles). After completion
of a full auto-zero and linearity calibration, the Sequencer
fetches the next instruction as pointed to by the Instruction
RAM’s pointer and resumes execution. If the Sequencer is
stopped, a full calibration is performed immediately at the
time requested.
Bit 4 is the Standby bit. Writing a “1” to Bit 4 immediately
places the LM12(H)454/8 in Standby mode. Normal opera-
tion returns when Bit 4 is reset to a “0”. The Standby com-
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