參數(shù)資料
型號(hào)： LM12H458MWG/883
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, CDFP44
文件頁(yè)數(shù)： 11/43頁(yè)
文件大小： 991K
代理商： LM12H458MWG/883
Timing Diagrams V
A+ = VD+ = +5V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, D0– D15 outputs.
1, 3: CS or Address valid to ALE low set-up time.
2, 4: CS or Address valid to ALE low hold time.
5: ALE pulse width
6: RD high to next ALE high
7: ALE low to RD low
8: RD pulse width
9: RD high to next RD or WR low
10: ALE low to WR low
11: WR pulse width
12: WR high to next ALE high
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
18: RD low to data valid (access time)
DS011264-16
FIGURE 10. Multiplexed Data Bus
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