參數(shù)資料
型號: LM1253A
廠商: National Semiconductor Corporation
英文描述: Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator
中文描述: 單片三180兆赫的I2C顯像管預(yù)先集成在屏幕顯示(OSD)發(fā)生器模擬放大器
文件頁數(shù): 7/57頁
文件大?。?/td> 1621K
代理商: LM1253A
External Interface Signals Electrical Characteristics
(Continued)
(See Figure 3 for Test Circuit)
Unless otherwise noted: V
CC
= +5V, V
IN
= 0.7V, C
L
= 8 pF, Video Signal Output = 1 V
PP
, T
A
= 25C, V
ABL
= V
CC
.
Symbol
Parameter
Conditions
LM1253A
Typ
3.9
Units
Min
Max
V
CCDET
F
FREE_RUN
V
IL
V
CC
Undervoltage Detection Threshold
Free Run HBLANK Frequency
Low Level Input Voltage for SDA and SCL
Pins
High Level Input Voltage for SDA and SCL
Pins
Low Level Output Voltage for SDA and SCL
Pins
V
30
60
kHz
1.5
V
V
IH
3
V
V
OL
3 mA Sink Current
0
0.4
V
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2:
Operating Ranges indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
change when the device is not operated under the listed test conditions.
Note 3:
All voltages are measured with respect to GND, unless otherwise specified.
Note 4:
Linearity Error = 100
*
(step
max
–step
min
)/step
ave
Where: The input signal is a 16 step staircase signal waveform with 0.7 V
P-P
level, subdivided into 16 equal steps, with each step approximately 100 ns in width
step
max
is the maximum voltage step at the output
step
min
is the minimum voltage step at the output
step
ave
is the average voltage of the 16 steps at the output.
Note 5:
Input from signal generator: t
r
, t
f
<
1 ns.
Note 6:
ABL should provide smooth decrease in gain over the operational range of 0 dB to 5 dB
A
ABL
= A(V
ABL
= V
ABL MAX GAIN
)–A (V
ABL
= V
ABL MIN GAIN
)
Test Circuit
DS101265-3
Note: 8 pF load includes parasitic capacitance
FIGURE 3. Test Circuit
L
www.national.com
7
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