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參數(shù)資料
| 型號： | LM12438CIWMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 27/80頁 |
| 文件大?。?/td> | 1552K |
| 代理商： | LM12438CIWMX |
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60 Operational Information (Continued)
FIFO REGISTER
(Read only)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Instruction Number
Sign
Conversion Result
or Extended Sign
D11 – D0
Conversion Result
For 12-bit a sign 12-bit result value
For
8-bit a sign D11 – D4 e result value D3 – D0 e 1110
D12
Sign Conversion result sign bit 0 e Positive 1 e Negative
D15 – D13 Instruction number associated with the conversion result or the extended sign bit for 2’s complement arithmetic
selected by bit D5 (Channel Mask) of the Configuration register
INTERRUPT STATUS REGISTER
(Read only)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Number of Unread Results
Instruction Number
INST7
X
INST5
INST4
INST3
INST2
INST1
INST0
in FIFO
Being Executed
Bits
0 to 7 are interrupt flags (vectors) that will be set to 1 when the following conditions occur The bits are set to 1 whether
the interrupt is enabled or disabled in the Interrupt Enable register The bits are reset to 0 when the register is read or by a
device reset through the Configuration register
D0
INST0 Is set to 1 when a limit is passed in watchdog mode
D1
INST1 Is set to 1 when the sequencer has loaded the instruction number contained in bits D10 D9 and D8 of the
Interrupt Enable register
D2
INST2 Is set to 1 when number of conversion results in FIFO is equal to the programmed value (D15 – D11) in the
Interrupt Enable Register
D3
INST3 Is set to 1 when an auto-zero cycle is completed
D4
INST4 Is set to 1 when a full calibraton cycle is completed
D5
INST5 Is set to 1 when a pause condition is encountered
D6
Don’t care
D7
INST7 Is set to 1 when the chip is returned from standby and is ready
D10 – D8
Holds the instruction number presently being executed or will be executed following a Pause or Timer delay
D15 – D11 Holds the number of conversion results that have been put in the FIFO but that have not yet been read by the user
LIMIT STATUS REGISTER
(Read only)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Limit
2 Status
Limit
1 Status
The bits in this register are limit flags (vectors) that will be set to 1 when a limit is passed The bits are associated to individual
instruction limits as indicated below
D0
Limit
1 of Instruction
0 is passed
D1
Limit
1 of Instruction
1 is passed
D2
Limit
1 of Instruction
2 is passed
D3
Limit
1 of Instruction
3 is passed
D4
Limit
1 of Instruction
4 is passed
D5
Limit
1 of Instruction
5 is passed
D6
Limit
1 of Instruction
6 is passed
D7
Limit
1 of Instruction
7 is passed
D8
Limit
2 of Instruction
0 is passed
D9
Limit
2 of Instruction
1 is passed
D10 Limit
2 of Instruction
2 is passed
D11 Limit
2 of Instruction
3 is passed
D12 Limit
2 of Instruction
4 is passed
D13 Limit
2 of Instruction
5 is passed
D14 Limit
2 of Instruction
6 is passed
D15 Limit
2 of Instruction
7 is passed
FIGURE 9 Bit Assignments for LM12434 and LM12 L 438 Internal Registers
(Continued)
33
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