參數(shù)資料
型號： LM12438CIWMX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： SOP-28
文件頁數(shù)： 24/80頁
文件大小： 1552K
代理商： LM12438CIWMX
60 Operational Information (Continued)
A4 A3 A2 A1
Purpose
Type D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0000
Instruction RAM
RW
Acquisition
Watch-
SH INb
SH INa
to
(RAM Pointer e 00)
Time
dog
812 Timer Sync
(MUXINb)
(MUXINa)
Pause
Loop
0111
0000
Instruction RAM
RW
to
(RAM Pointer e 01)
Don’t Care
l
k
Sign
Limit
1
0111
0000
Instruction RAM
RW
to
(RAM Pointer e 10)
Don’t Care
l
k
Sign
Limit
2
0111
1000
Configuration
RW
Don’t Care
DIAG
Test
RAM
SYNC AZ Each
IS
Stand-
Full
Auto-
Reset
Start
Register
e
0
Pointer
IO
Cycle
by
CAL
Zero
Interrupt Enable
Register
RW
Generate Interrupt (INT2)
Number of Conversion
Results in FIFO to
Instruction
INT7
X
INT5
INT4
INT3
INT2
INT1
INT0
1001
Number to
Generate
Interrupt (INT1)
Interrupt Status
Register
R
Conversion Results
Number of Unread
in FIFO
Instruction
INST7
X
INST5 INST4 INST3 INST2 INST1 INST0
1010
Number
being
Executed
1011
Timer
RW
Timer Preset High Byte
Timer Preset Low Byte
Register
1100
Conversion
FIFO
R
Instruction
Sign
Data MSBs
Conversion
Conversion Data LSBs
Number or
Extended
Sign
1101
Limit Status
R
Limit
2 Status
Limit
1 Status
Register
LM12434 (Refer to Table IV)
LM12 L 438 only Must be set to ‘‘0’’ for the LM12434
X No interrupt is associated with this bit When programming the interrupt Enable Register bit-6 is a don’t care condition
FIGURE 9 Bit Assignments for LM12434 and LM12 L 438 Internal Registers
30
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PDF描述
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