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參數(shù)資料
| 型號： | LH7A404N0F092B3 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 32-Bit System-on-Chip |
| 封裝： | LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT |
| 文件頁數(shù)： | 28/75頁 |
| 文件大小： | 1109K |
| 代理商： | LH7A404N0F092B3 |
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LH7A404
32-Bit System-on-Chip
28
Preliminary data sheet
NXP Semiconductors
Battery voltage sense in addition to normal direct
voltage inputs
A 9-channel multiplexer for routing user-selected
inputs to A/D
A 16 × 16 FIFO for 10-bit digital output of A/D
A pen-down sensor to generate interrupts to the host
Low-power circuitry and power control modes to
minimize on-chip power dissipation
Conversion automation for flexibility while minimizing
CPU management and interrupt overhead
A brownout detector with separate interrupt
Battery Monitor Interface (BMI)
The BMI is a serial communication interface speci-
fied for two types of battery monitors/gas gauges. The
first type employs a single wire interface. The second
interface employs a two-wire multi-master bus, imple-
menting the Smart Battery System Specification.
If both interfaces are enabled at the same time, the
Single Wire Interface has priority.
SINGLE WIRE INTERFACE
The Single Wire Interface performs:
Serial-to-parallel conversion on data received from
the peripheral device
Parallel-to-serial conversion on data transmitted to
the peripheral device
Data packet coding/decoding on data transfers
(incorporating Start/Data/Stop data packets)
The Single Wire interface uses a command-based
protocol in which the host initiates a data transfer by
sending a WriteData/Command word to the battery
monitor.
SMART BATTERY INTERFACE
The Smart Battery Interface performs:
Serial-to-parallel conversion on data received from
the peripheral device
Parallel-to-serial conversion of data transmitted to
the peripheral device.
The Smart Battery Interface uses a two-wire multi-
master bus (the SMBus), allowing multiple bus masters
to be connected to it. A master device initiates a bus
transfer and provides the clock signals. A slave device
can receive data provided by the master or it can pro-
vide data to the master. Since more than one device
may attempt to take control of the bus as a master,
SMBus provides an arbitration mechanism by relying
on the wired-AND connection of all SMBus interfaces
to the SMBus.
DC-to-DC Converter
The features of the DC-DC Converter interface are:
Dual-drive PWM outputs with independent closed
loop feedback
Software programmable configuration of one of 8
output frequencies (each being a fixed division of the
input clock).
Software programmable configuration of duty cycle
from 0 to 15/16, in intervals of 1/16.
Hardware-configured output polarity (for positive or
negative voltage generation) during power-on reset
via the polarity select inputs
Dynamically switched PWM outputs to one of a pair
of preprogrammed frequency/duty cycle combina-
tions via external pins.
Watchdog Timer (WDT)
The Watchdog Timer provides hardware protection
against malfunctions. It is a programmable timer that is
reset by software at regular intervals. Failure to reset
the timer will cause an FIQ interrupt. Failure to service
the FIQ interrupt generates a system reset.
Features of the WDT:
Timing derived from the system clock
16 programmable time-out periods: 2
16
through 2
31
clock cycles
Generates a system reset (resets LH7A404) or a
FIQ interrupt whenever a time-out period is reached
Software enable, lockout, and counter-reset mecha-
nisms add security against inadvertent writes
Protection mechanism guards against interrupt-
service-failure:
– The first WDT time-out triggers FIQ and asserts
nWDFIQ status flag
– If FIQ service routine fails to clear nWDFIQ, then
the next WDT time-out triggers a system reset.
General Purpose I/O (GPIO)
The GPIO has eight ports, each with a data register
and a data direction register. It also has added regis-
ters including Keyboard Scan, PINMUX, GPIO Inter-
rupt Enable, INTYPE1/2, GPIOFEOI and PGHCON.
The data direction register determines whether a
port is configured as an input or an output while the
data register is used to read the value of the GPIO pins.
The GPIO Interrupt Enable, INTYPE[2:1], and the
GPIOFEOI registers control edge-triggered Interrupts
on Port F. The PINMUX register controls which signals
are from Port D and Port E when they are set as out-
puts, while the PGHCON controls the operations of
Port G and Port H.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH7A404N0F092B3,55 | 功能描述:ARM微控制器 - MCU LCD,USB FS/HOST,MMU,ADC,BGA324 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH7A404N0F092B3,551 | 制造商:NXP Semiconductors 功能描述:LH7A404 Series 3.6 V 266 MHZ Surface Mount 32-Bit System-on-Chip |
| LH7A404N0F092B3;55 | 功能描述:ARM微控制器 - MCU LCD USB FS/HOST MMU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH7A404N0F092B3-S | 功能描述:ARM微控制器 - MCU ARM9 LCD USB HOST RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH7A405 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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