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參數(shù)資料
| 型號(hào)： | LH79531 |
| 英文描述： | ARM RISC CORE ASSPs ARM7TDMI |
| 中文描述： | ARM的RISC核心專用標(biāo)準(zhǔn)的ARM7TDMI |
| 文件頁(yè)數(shù)： | 16/39頁(yè) |
| 文件大?。?/td> | 296K |
| 代理商： | LH79531 |
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LH79520
System-on-Chip
16
8/21/02
Preliminary Data Sheet
Memory Architecture
An integrated SDRAM Controller and Static Memory
Controller provide a glueless interface to external
SDRAM, Flash, SRAM, ROM, and burst ROM. Three
remap options for the physical memory are selectable
by software, as shown in Figures 4, 5, and 6. Memory
is exclusively Little Endian.
SDRAM CONTROLLER
The SDRAM Controller provides the interface
between the internal bus and external (off-chip)
SDRAM memory devices (Figure 2).
The SDRAM Controller provides the following features:
Two independently controlled chip selects.
Transfers data between the controller and SDRAM
in quad-word bursts.
Supports both 32-bit and 16-bit SDRAM.
Supports 2K, 4K, and 8K row address memory parts,
i.e. typical 256M, 128M, 64M, and 16M parts, with 8,
16, or 32 DQ bits per device.
Two reset domains allow SDRAM contents to be
preserved over a soft reset.
STATIC MEMORY CONTROLLER (SMC)
The SMC provides the interface between the internal
bus and external (off-chip) memory devices.
The LH79520 boots from 16-bit memory. The SMC
address space is divided into eight memory banks of
64MB each. The SMC supports:
Static Memory-mapped Devices including RAM,
ROM, Flash, and Burst ROM
Asynchronous Operations:
– Page Mode Reads for non-clocked memory
– Burst Mode Reads for burst mode ROM
8-, 16-, and 32-bit wide external memory data paths
Independent configuration for up to eight memory
banks, each up to 64MB
Programmable Parameters:
– WAIT States (up to 32)
– Bus Turnaround Cycles (1 to 16)
– Initial and Subsequent Burst Read WAIT State for
Burst ROM Devices.
The Static Memory Controller (SMC) also supports
an nWAIT input that can be used by an external device
to vary the wait time.
DMA Controller
The DMA Controller provides support for DMA-
capable peripherals. The LCD controller uses its own
DMA port, connecting directly to memory for retrieving
display data.
Figure 4. Memory Remap ‘00’ and ‘11’
Figure 5. Memory Remap ‘10’
Figure 6. Memory Remap ‘01’
79520-5
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
ADVANCED PERIPHERAL BUS
PERIPHERALS
RESERVED
EXTERNAL STATIC MEMORY
EXTERNAL STATIC MEMORY
SDRAM
INTERNAL STATIC MEMORY
0xFFFFFFFF
0xFFFF0000
0xFFFC0000
0x80000000
0x60000000
0x40000000
0x20000000
0x00000000
79520-4
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
ADVANCED PERIPHERAL BUS
PERIPHERALS
RESERVED
INTERNAL STATIC MEMORY
EXTERNAL STATIC MEMORY
SDRAM
INTERNAL STATIC MEMORY
0xFFFFFFFF
0xFFFF0000
0xFFFC0000
0x80000000
0x60000000
0x40000000
0x20000000
0x00000000
79520-3
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
ADVANCED PERIPHERAL BUS
PERIPHERALS
RESERVED
SDRAM
EXTERNAL STATIC MEMORY
SDRAM
INTERNAL STATIC MEMORY
0xFFFFFFFF
0xFFFF0000
0xFFFC0000
0x80000000
0x60000000
0x40000000
0x20000000
0x00000000
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