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參數(shù)資料
| 型號(hào)： | LH5PV16256 |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 4M (256K x 16) Pseudo-Static RAM |
| 中文描述： | 的CMOS 4分（256K × 16），偽靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | LH5PV16256 |
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NOTES:
1.
AC characteristics are measured at t
T
= 5 ns.
2.
AC characteristics are measured at the following condition:
3.
Row address signals are latched in the memory at the falling edge of CE.
4.
5.
Measured with a load equivalent to 50 pF.
Input data is latched in the memory at the earlier rising edge of CE and UWE/LWE. One of (t
AHW
, t
DSW
, t
DHW
) and (t
AHC
, t
DSC
, t
DHC
) needs
to be satisfied. The other is "Don’t care."
Address refresh or auto refresh is needed to be executed 2,048 times within 32 ms.
In order to initialize the internal circuits, an initial pause of 500
μ
s with CE = RFSH = V
IH
is required after power-up, and followed by at
least 8 dummy cycles. When supply voltage falls down below the recommended supply voltage by temporarily power-down, a waiting time
is required at V
= 0 V for more than 400 ms before power-up, and a pause of 500
μ
s with CE = RFSH = V
IH
and 8 dummy cycles are
also necessary after power-up.
Auto refresh and self refresh are defined by RFSH pulse width during CE = V
IH
. If RFSH pulse width is shorter than t
FAP
(MAX.), the cycle
is an auto refresh cycle and memory cells are refreshed by an internal counter. If RFSH pulse width is longer than t
FAS
(MIN.), the cycle
is a self refresh cycle and memory cells are refreshed by an internal clock generator automatically.
t
RCH
and t
WHZ
are determined by the earlier falling edge of UWE and LWE.
10. t
WCS
is determined by the later falling edge of UWE and LWE.
11. t
RCS
, t
WLZ
, and t
DHW
are determined by the later rising edge of UWE and LWE.
12. t
WCH
and t
DSW
are determined by the earlier rising edge of UWE and LWE.
13. t
WHZ
, t
WCP
, t
WCS
, t
WCH
, t
DSW
, t
DHW
, t
WLZ
, and t
AHW
should be satisfied by both UWE and LWE.
14. The transition time of the supply voltage in data retention mode is less than 0.05 V/ms.
15. The width of data retention period is more than t
FAS
(MIN.) like self-refresh cycle.
16. All input pins are required to be higher than -0.3 V.
17. RFSH must be lower than 0.2 V during the data retention period.
18. CE and CS must be higher than V
CC
- 0.2 V during the data retention period.
6.
7.
8.
9.
INPUT
2.2 V
0.8 V
2.4 V
0.4 V
2.0 V
0.8 V
5PV16256S-13
OUTPUT
Figure 3. AC Characteristics
LH5PV16256
CMOS 4M (256
×
16) Pseudo-Static RAM
6
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