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| 型號： | LH543601P-35 |
| 廠商： | Sharp Corporation |
| 英文描述： | 256 x 36 x 2 Bidirectional FIFO |
| 中文描述： | 256 × 36 × 2雙向先進先出 |
| 文件頁數(shù)： | 9/43頁 |
| 文件大小： | 360K |
| 代理商： | LH543601P-35 |
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AC ELECTRICAL CHARACTERISTICS
1
(V
CC
= 5 V
±
10%, T
A
= 0
°
C to 70
°
C)
SYMBOL
DECRIPTION
–20
–25
–30
–35
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
CC
t
CC
t
CH
t
CL
t
DS
t
DH
t
ES
t
EH
t
RWS
t
RWH
t
RQS
t
RQH
t
AS
t
AH
t
A
t
ACK
t
OH
Clock Cycle Frequency
—
50
—
40
—
33
—
28.5
MHz
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
20
8
8
—
—
—
25
10
10
—
—
—
30
12
12
—
—
—
35
15
15
—
—
—
ns
ns
ns
Data Setup Time
Data Hold Time
Enable Setup Time
10
0
—
—
12
0
—
—
13
0
—
—
15
0
—
—
ns
ns
10.4
0
10.4
—
—
—
13
0
13
—
—
—
15
0
15
—
—
—
15
0
18
—
—
—
ns
ns
ns
Enable Hold Time
Read/Write Setup Time
Read/Write Hold Time
Request Setup Time
Request Hold Time
Address Setup Time
6
Address Hold Time
6
Data Output Access Time
0
12
0
—
—
—
0
15
0
—
—
—
0
18
0
—
—
—
0
21
0
—
—
—
ns
ns
ns
12
0
—
—
—
12.8
15
0
—
—
—
16
18
0
—
—
—
20
21
0
—
—
—
25
ns
ns
ns
Acknowledge Access Time
Output Hold Time
Output Enable Time, OE LOW to D
0
– D
35
Low-Z
2
Output Disable Time, OE HIGH to
D
0
– D
35
High-Z
2
Clock to EF Flag Valid (Empty Flag)
—
2.0
12
—
—
2.0
15
—
—
2.0
20
—
—
2.0
25
—
ns
ns
t
ZX
1.5
—
2.0
—
3.0
—
3.0
—
ns
t
XZ
—
9
—
12
—
15
—
20
ns
t
EF
t
FF
t
HF
—
17.6
—
22
—
25
—
30
ns
Clock to FF Flag Valid (Full Flag)
Clock to HF Flag Valid (Half-Full)
Clock to AE Flag Valid (Almost-
Empty)
—
—
17.6
17.6
—
—
22
22
—
—
25
25
—
—
30
30
ns
ns
t
AE
—
16
—
20
—
25
—
30
ns
t
AF
Clock to AF Flag Valid (Almost-Full)
Clock to MBF Flag Valid (Mailbox
Flag)
—
16
—
20
—
25
—
30
ns
t
MBF
—
12
—
15
—
20
—
25
ns
t
PF
t
RS
t
RSS
t
RSH
t
RF
t
FRL
t
FWL
t
BS
t
BH
t
BA
Data to Parity Flag Valid
Reset/Retransmit Pulse Width
7
Reset/Retransmit Setup Time
3
Reset/Retransmit Hold Time
3
Reset LOW to Flag Valid
First Read Latency
4
First Write Latency
5
Bypass Data Setup
—
13.6
—
—
—
17
—
—
—
20
—
—
—
25
—
—
ns
ns
ns
32/20
16
40/25
20
52/30
25
65/35
30
8
—
—
28
10
—
—
35
15
—
—
40
20
—
—
45
ns
ns
20
20
12
—
—
—
25
25
15
—
—
—
30
30
18
—
—
—
35
35
21
—
—
—
ns
ns
ns
Bypass Data Hold
Bypass Data Access
3
—
—
18
5
—
—
20
5
—
—
25
5
—
—
30
ns
ns
NOTES:
1.
Timing measurements performed at ‘AC Test Condition’ levels.
2.
Values are guaranteed by design; not currently production tested.
3.
t
RSS
and/or t
RSH
need not be met unless a rising edge of CK
A
occurs while EN
A
is being asserted, or else a rising edge of CK
B
occurs while
EN
B
is being asserted.
4.
t
FRL
is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data.
5.
t
FWL
is the minimum first-read-to-first-write delay, following a full condtion, which is required to assure successful writing of data.
256
×
36
×
2 Bidirectional FIFO
LH543601
9
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