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參數(shù)資料
| 型號： | LH543601P-35 |
| 廠商： | Sharp Corporation |
| 英文描述： | 256 x 36 x 2 Bidirectional FIFO |
| 中文描述： | 256 × 36 × 2雙向先進先出 |
| 文件頁數(shù)： | 15/43頁 |
| 文件大小： | 360K |
| 代理商： | LH543601P-35 |
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18-Bit Data Streams
36-Bit Data Stream
18
18
18
18
Bits 18-35
(2nd Halfword)
Bits 18-35
(2nd Halfword)
(1st Halfword)
Bits 0-17
(1st Halfword)
2nd Halfword, then 1st Halfword
1st Halfword, then 2nd Halfword
D
35A
D
18A
D
17A
D
0A
D
35B
D
18B
D
17B
D
0B
PORT
A
PORT
B
543601-32
Figure 6a. 36-to-18 Funneling Through FIFO #1
9-Bit Data Streams
36-Bit Data Stream
9
9
9
9
Bits 27-35
(4th Byte)
4th Byte, then 1st Byte, then 2nd Byte, then 3rd Byte
D
35A
D
27A
D
26A
D
18A
D
35B
D
27B
D
26B
D
18B
PORT
A
PORT
B
9
9
9
9
D
17A
D
9A
D
8A
D
0A
D
17B
D
9B
D
8B
D
0B
Bits 18-26
(3rd Byte)
Bits 9-17
(2nd Byte)
Bits 0-8
(1st Byte)
3rd Byte, then 4th Byte, then 1st Byte, then 2nd Byte
2nd Byte, then 3rd Byte, then 4th Byte, then 1st Byte
1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte
543601-34
Figure 6b. 36-to-9 Funneling Through FIFO #1
PORT B WORD-WIDTH SELECTION
NOTES:
1.
The heavy black borders on register segments indicate the main
data path, suitable for most applications. Alternate paths feature
a different ordering of bytes within a word, at Port B.
2.
The funneling process does not change the ordering of bits within
a byte. Halfwords (Figure 6a) or bytes (Figure 6b) are trans-
ferred in parallel form from Port A to Port B.
3.
The word-width setting may be changed during system operation;
however, two clock intervals should be allowed for these signals
to settle, before again attempting to read D
– D
, and three
dummy words should be passed through initially. Also, incom-
plete data words may occur, when the word width is changed
from shorter to longer at an inappropriate point in the data block
passing through the FIFO.
256
×
36
×
2 Bidirectional FIFO
LH543601
15
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