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參數(shù)資料
| 型號： | LH540202 |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 1024 x 9 Asynchronous FIFO |
| 中文描述： | 1024 × 9的CMOS異步FIFO |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 156K |
| 代理商： | LH540202 |
OPERATIONAL MODES (cont’d)
Depth Cascading
Depth cascading is implemented by configuring the
required number of LH540202s in depth-cascaded mode.
In this arrangement, the FIFOs are connected in a circular
fashion, with the Expansion Out output (XO) of each
device tied to the Expansion In input (XI) of the next
device. One FIFO in the cascade must be designated as
the ‘first-load’ device, by tying its First Load input (FL/RT)
to ground. All other devices must have their FL/RT inputs
tied HIGH. In this mode, W and R signals are shared by
all devices, while logic within each LH540202 controls the
steering of data. Only one LH540202 is enabled during
any given write cycle; thus, the common Data In inputs of
all devices are tied together. Likewise, only one
LH540202 is enabled during any given read cycle; thus,
the common Data Out outputs of all devices are wire-
ORed together
In depth-cascaded mode, external logic should be
used to generate a composite Full Flag and a composite
Empty Flag, by ANDing the FF outputs of all LH540202
devices together and ANDing the EF outputs of all devices
together. Since FF and EF are assertive-LOW signals,
this ‘ANDing’ actually is implemented using an assertive-
HIGH physical OR gate. The Half-Full Flag and the
Retransmit function are not available in depth-cascaded
mode.
RS
RS
FF
9
9
RS
W
FF
DATA IN
D
0
- D
8
RS
FF
9
9
9
R
DATA OUT
Q
0
- Q
8
9
FL
FL
EF
XI
XO
FL
EF
Vcc
Vcc
XO
XO
9
9
XI
540202-19
XI
EMPTY
FULL
EF
LH540202
LH540202
LH540202
Figure 6. FIFO Depth Cascading
(3072
×
9)
LH540202
CMOS 1024
×
9 Asynchronous FIFO
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH540203U15 | CMOS 2048X9 ASYNCHRONOUS FIFO |
| LH540203 | CMOS 2048 x 9 Asynchronous FIFO |
| LH540204 | CMOS 4096 x 9 Asynchronous FIFO |
| LH540205 | CMOS 8192 x 9 Asynchronous FIFO |
| LH540215 | 512 x 18 / 1024 x 18 Synchronous FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH540202-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540202-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540202-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540202-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| LH540202-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
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