參數(shù)資料
型號: LH28F640SPHT-PTL12
廠商: Sharp Corporation
英文描述: 64Mbit (4Mbitx16/8Mbitx8) Page Flash Memory
中文描述: 64兆比特(4Mbitx16/8Mbitx8)頁閃存
文件頁數(shù): 22/45頁
文件大?。?/td> 1041K
代理商: LH28F640SPHT-PTL12
LHF64P01 20
1.2.4 AC Characteristics - Read-Only Operations
(1)
NOTES:
1. Refer to AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. OE# may be delayed up to t
ELQV
t
GLQV
after the first edge of CE
0
, CE
1
or CE
2
that enables the device
(refer to Table 2) without impact to t
ELQV
.
4. The timing is defined from the first edge of CE
0
, CE
1
or CE
2
that enables the device.
5. The timing is defined from the first edge of CE
0
, CE
1
or CE
2
that disables the device.
T
A
=-40
°
C to +85
°
C
V
CC
V
CCQ
Notes
3.0V-3.6V
2.7V-3.6V
3.0V-3.6V
2.7V-3.6V
Symbol
t
AVAV
t
AVQV
t
ELQV
t
APA
t
GLQV
t
PHQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
Parameter
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
120
120
ns
Address to Output Delay
120
120
ns
CE
X
to Output Delay
3, 4
120
120
ns
Page Address Access Time
25
30
ns
OE# to Output Delay
3
25
30
ns
RP# High to Output Delay
180
180
ns
CE
X
to Output in Low Z
2, 4
0
0
ns
OE# to Output in Low Z
2
0
0
ns
CE
X
to Output in High Z
2, 5
35
35
ns
OE# to Output in High Z
2
15
15
ns
t
OH
Output Hold from First Occurring Address, CE
X
or OE#
change
2, 5
0
0
ns
t
ELFL
/t
ELFH
t
FLQV
/t
FHQV
t
FLQZ
/t
FHQZ
CEx Setup to BYTE# Going Low or High
2, 4
10
10
ns
BYTE# to Output Delay
1000
1000
ns
BYTE# to Output in High Z
2
1000
1000
ns
Rev. 0.06
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