參數(shù)資料
型號(hào)： LH28F640BFHE-PBTL80
英文描述： Flash ROM
中文描述： 閃存ROM
文件頁(yè)數(shù)： 34/56頁(yè)
文件大小： 373K
代理商： LH28F640BFHE-PBTL80
- 34 -
LH28F160S5-L/S5H-L
RY/BY# mode) will remain low until the reset
operation is complete. Then, the operation will abort
and the device will enter deep power-down. The
aborted operation may leave data partially altered.
Therefore, the command sequence must be
repeated after normal operation is restored. Device
power-off or RP# transitions to V
IL
clear the status
register.
The CUI latches commands issued by system
software and is not altered by V
PP
or CE#
transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep power-
down or after V
CC
transitions below V
LKO
.
After block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration, even after V
PP
transitions down to V
PPLK
, the CUI must be placed
in read array mode via the Read Array command if
subsequent access to the memory array is desired.
5.6
The device is designed to offer protection against
accidental block and full chip erasure, (multi)
word/byte writing or block lock-bit configuration
during power transitions. Upon power-up, the
device is indifferent as to which power supply (V
PP
or V
CC
) powers-up first. Internal circuitry resets the
CUI to read array mode at power-up.
Power-Up/Down Protection
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is
active. Since both WE# and CE# must be low for a
command write, driving either to V
IH
will inhibit
writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP# = V
IL
regardless of its control inputs
state.
5.7
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
Power Consumption
In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solid-
state storage can consume negligible power by
lowering RP# to V
IL
standby or sleep modes. If
access is again needed, the devices can be read
following the t
PHQV
and t
PHWL
wake-up cycles
required after RP# is first raised to V
IH
. See
Section
6.2.4 through 6.2.6
"
AC CHARACTERISTICS -
READ-ONLY and WRITE OPERATIONS"
and
Fig. 15
,
Fig. 16
,
Fig. 17
and
Fig. 18
for more
information.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LH28F640BFHE-PBTL90 制造商:Sharp Microelectronics 功能描述:NOR Flash Parallel 3V 64Mbit 4M x 16bit 90ns 48-Pin TSOP 制造商:Sharp Microelectronics Corporation 功能描述:NOR Flash Parallel 3V 64Mbit 4M x 16bit 90ns 48-Pin TSOP
LH28F640BFHE-PBTLDY 制造商:Sharp Microelectronics 功能描述:64M 90ns Access time Smart Bottom Boot Block
LH28F640BFHE-PBTLHGA 制造商:Sharp Microelectronics Corporation 功能描述:64M (4MX16) 3V, BOOT BLOCK, BOT, TSOP48, IND, HAZMAT - Trays
LH28F640BFHE-PTTL60 制造商:Sharp Microelectronics Corporation 功能描述:FLASH PARALLEL 3V/3.3V 64MBIT 4MX16 60NS 48TSOP - Trays
LH28F640BFHE-PTTL80 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM
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