參數(shù)資料
型號: LH28F320S5H-L
廠商: Sharp Corporation
英文描述: 32M-BIT ( 2Mbit x16 / 4Mbit x8 )Boot Block Flash MEMORY(32M位( 2M位 x16 / 4M位 x8 )Boot Block 閃速存儲器)
中文描述: 32兆位(2Mbit的x16 /的4Mb × 8)啟動塊閃存(32兆位(200萬位x16 / 4分位× 8)啟動塊閃速存儲器)
文件頁數(shù): 5/50頁
文件大?。?/td> 338K
代理商: LH28F320S5H-L
PRELMNARY
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, full chip erase, (multi)
LH28F320S5-L/S5H-L
1 INTRODUCTION
This datasheet contains LH28F320S5-L/S5H-L
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. The LH28F320S5-L/
S5H-L flash memories documentation also includes
ordering information which is referenced in
Section 7.
1.1
The LH28F320S5-L/S5H-L are high-performance
32 M-bit Smart 5 flash memories organized as
4 MB x 8/2 MB x 16. The 4 MB of data is arranged
in sixty-four 64 k-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in
Fig. 1
.
Product Overview
Smart 5 technology provides a choice of V
CC
and
V
PP
combination, as shown in
Table 1
, to meet
system performance and power expectations. V
PP
at 5 V eliminates the need for a separate 12 V
converter, while V
PP
= 5 V maximizes erase and
write performance. In addition to flexible erase and
program voltages, the dedicated V
PP
pin gives
complete data protection when V
PP
V
PPLK
.
Table 1 V
CC
and V
PP
Voltage Combination
Offered by Smart 5 Technology
V
CC
Voltage
5 V
Internal V
CC
and V
PP
detection circuitry auto-
matically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
word/byte write and block lock-bit configuration
operations.
A block erase operation erases one of the device’s
64 k-byte blocks typically within 0.34 second (5 V
V
, 5 V V
) independent of other blocks. Each
(6.4 million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
A word/byte write is performed in byte increments
typically within 9.24 μs (5 V V
CC
, 5 V V
PP
). A multi
word/byte write has high speed write performance
of 2 μs/byte (5 V V
CC
, 5 V V
PP
). (Multi) word/byte
write suspend mode enables the system to read
data from, or write data to any other flash memory
array location.
Individual block locking uses a combination of bits
and WP#, sixty-four block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or
block lock-bit configuration operation is finished.
The STS output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using STS
minimizes both CPU overhead and system power
consumption. STS pin can be configured to
different states using the Configuration command.
The STS pin defaults to RY/BY# operation. When
low, STS indicates that the WSM is performing a
V
PP
Voltage
5 V
- 5 -
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