12
LH155BA
Data Write Operation
n
n
n + 4
n + 1
n + 1
n + 2
n + 2
n + 3
n + 4
n + 3
D
7
-D
0
WRB
Internal
Bus
Holder
WRB
Data Read Operation
D
7
-D
0
WRB
Address Set
n Address
Data Read
n Address
Data Read
n + 1 Address
Data Read
n + 2 Address
Dummy
Read
RDB
n
***
n
n + 1
n + 2
2.2. Access to Display RAM and
Internal Register
The LH155BA makes access to display RAM, and
internal register by data bus D
7
to D
0
, chip
selection CSB pin, display RAM/register shifting
RS pin, and read/write control RDB and WRB pins.
When CSB is at "H", it is in non-selective state and
cannot access display RAM and internal registers.
When making access to them, set CSB to "L".
The access to either display RAM or internal
registers can be shifted by RS input.
RS = "L" : Display RAM data
RS = "H" : Internal command register
The data of 8-bit data bus D
7
to D
0
are written by
write-operation after address setting through MPU.
The timing of write is at the rising of WRB for 80-
family MPU and at the falling of E for 68-family
MPU respectively.
Write is internally processed by intermediately
placing the bus holder in the internal data bus.
During data writing from MPU, the data are
temporally held in the bus holder, then they are
written by the time of the next cycle.
Since the read sequence of display RAM data is
limited, note that when address set is made, the
designated address data are not output to read
command immediately after the address set, but
are output when the second data are read,
resulting in requiring one time dummy read.
Dummy read is always required one time after
address set and write cycle.