
LH155BA
27
The LH155BA has a lot of commands, as shown in
the list of commands, and each command is
explained in detail as follows.
Data codes and command codes are defined as
follows and the execution of commands must be
made in the chip selection state (CSB = "L").
(For example X address)
RS
*
0
Command Codes
* RS = "0" : RAM data access (Refer to
Sections 4.2. and 4.3.
.)
RS = "1" : Register access (Refer to
Sections 4.4. through 4.17.
.)
The undefined command codes are inhibited.
The display RAM data of 8-bit are written in the
designated X and Y addresses.
4.2. Data Write to Display RAM
D
6
D
7
The 8-bit contents of display RAM designated in X
and Y addresses are read out.
Immediately after data are set in X and Y
addresses, dummy read is necessary one time.
4.3. Data Read to Display RAM
D
6
D
7
D
4
0
D
5
0
D
6
0
D
7
AX0
D
0
AX1
D
1
AX2
D
2
AX3
D
3
Data Codes
D
0
CSB
0
D
1
D
2
D
3
D
4
D
5
Display RAM Write Data
D
0
D
1
D
2
D
3
D
4
D
5
Display RAM Read Data
RE
0
RDB
1
WRB
0
RS
0
CSB
0
RE
0
RDB
0
WRB
1
RS
0
(At the time of reset : AX3 to AX0 = 0
H
, read address : 0
H
)
4.4. X Address Register Set
D
6
D
7
0
0
Addresses of display RAM's X direction are set.
The values of AX3 to AX0 are usable up to 00
H
-
0F
H
, but 10
H
-FF
H
are inhibited. When the register
setting of SEG output normal/reverse is REF = "0",
the data of AX3 to AX0 are addressed to display
RAM as they are.
When REF = "1", the data of 0F
H
-(AX3 to AX0)
H
are addressed to the display RAM.
D
0
AX0
D
1
AX1
D
2
AX2
D
3
AX3
D
4
0
D
5
0
CSB
0
RE
0
RDB
1
WRB
0
RS
1