4-5
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Pin Information Summary
1 (Cont.)
XP10
XP15
XP20
Pin Type
256 fpBGA 388 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA
Single Ended User I/O
188
244
188
268
300
188
268
340
Differential Pair User I/O
2
76
104
76
112
128
76
112
144
Configuration
Dedicated
1111111111111111
Muxed
1414141414141414
TAP
5
555
5
Dedicated
(total without supplies)
6
666
6
VCC
814814
28814
28
VCCAUX
4
444
12
44
12
VCCPLL
2
222
2
VCCIO
Bank0
2
525
425
4
Bank1
2
525
425
4
Bank2
2
424
4
Bank3
2
424
4
Bank4
2
525
425
4
Bank5
2
525
425
4
Bank6
2
424
4
Bank7
2
424
4
GND
2450245056245056
GNDPLL
2
222
2
NC
0240
0400
0
Single Ended/
Differential I/O
per Bank
2
Bank0
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank1
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank2
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
Bank3
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
Bank4
26/11
33/14
26/11
39/16
40/17
39/16
47/20
Bank5
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank6
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
Bank7
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
VCCJ
1
111
1
1. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table for
more information.