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參數(shù)資料
| 型號(hào)： | LFX200C-4F900C |
| 廠商： | Lattice Semiconductor Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; Body Material:Aluminum Alloy; Series:MS3112; No. of Contacts:8; Connector Shell Size:16; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle; Circular Contact Gender:Pin RoHS Compliant: No |
| 中文描述： | 在ispXPGA架構(gòu) |
| 文件頁(yè)數(shù)： | 39/89頁(yè) |
| 文件大?。?/td> | 941K |
| 代理商： | LFX200C-4F900C |
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Lattice Semiconductor
ispXPGA Family Data Sheet
39
ispXP sysCONFIG Port Timing Speci
fi
cations
Boundary Scan Timing
Symbol
Timing Parameter
Min.
Typ.
Max.
Units
sysCONFIG Write Cycle Timing
t
SUCS
t
HCS
t
SUWD
t
HWD
t
PRGM
t
WINIT
t
IODISS
t
WRDY
t
IOENSS
t
WH
t
WL
f
MAXW
sysCONFIG Read Cycle Timing
Input setup time of CS to CCLK rise
12
—
—
ns
Hold time of CS to CCLK Rise
0
—
—
ns
Input setup time of write data to CCLK rise
12
—
—
ns
Hold time of write data to CCLK rise
0
—
—
ns
Low time to reset device SRAM
5
—
50
ns
INIT pulse width
4
—
—
ms
User I/O disable
—
—
30
ns
Time to write data into SRAM
—
—
4
ms
User I/O enable
—
—
30
ns
Write clock High pulse width
12
—
—
ns
Write clock Low pulse width
12
—
—
ns
Write f
MAX
—
—
25
MHz
t
HREAD
t
SUREAD
t
RH
t
RL
f
MAXR
t
CORD
Hold time of READ to CCLK rise
0
—
—
ns
Input setup time of READ High to CCLK rise
30
—
—
ns
READ clock high pulse width
12
—
—
ns
READ clock low pulse width
15
—
—
ns
Read f
MAX
Clock to out for read data
—
—
25
MHz
—
—
25
ns
Parameter
Description
Min.
Max.
Units
t
BTCP
t
BTCPH
t
BTCPL
t
BTS
t
BTH
t
BTRF
t
BTCO
t
BTCODIS
t
BTCOEN
t
BTCRS
t
BTCRH
t
BUTCO
t
BTUODIS
t
BTUPOEN
TCK [BSCAN] Clock Pulse Width
40
—
ns
TCK [BSCAN] Clock Pulse Width High
20
—
ns
TCK [BSCAN] Clock Pulse Width Low
20
—
ns
TCK [BSCAN] Setup Time
8
—
ns
TCK [BSCAN] Hold Time
10
—
ns
TCK [BSCAN] Rise/Fall Time
50
—
mV/ns
TAP Controller Falling Edge of Clock to Valid Output
—
18
ns
TAP Controller Falling Edge of Clock to Valid Disable
—
18
ns
TAP Controller Falling Edge of Clock to Valid Enable
—
18
ns
BSCAN Test Capture Register Setup Time
8
—
ns
BSCAN Test Capture Register Hold Time
25
—
ns
BSCAN Test Update Register, Falling Edge of Clock to Valid Output
—
45
ns
BSCAN Test Update Register, Falling Edge of Clock to Valid Disable
—
20
ns
BSCAN Test Update Register, Falling Edge of Clock to Valid Enable
—
20
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFX500C-4F900C | PT 8C 8#16 SKT RECP |
| LFX125B-3F900C | The ispXPGA architecture |
| LFX200B-3F900C | The ispXPGA architecture |
| LFX500B-3F900C | The ispXPGA architecture |
| LFX125C-3F900C | The ispXPGA architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFX200C-4F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX200C-4FE680C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX200C-4FE680I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX200C-4FH516C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX200C-4FH516I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family |
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