參數(shù)資料
型號(hào)： LFX200C-3F900I
廠商： Lattice Semiconductor Corporation
英文描述： The ispXPGA architecture
中文描述： 在ispXPGA架構(gòu)
文件頁(yè)數(shù)： 32/89頁(yè)
文件大小： 941K
代理商： LFX200C-3F900I
Lattice Semiconductor
ispXPGA Family Data Sheet
32
sysHSI Block Timing
Figure 23 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on
a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance.
Figure 23. Receive Data Eye Diagram Template (Differential)
The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal
quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye
closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s
ability to transfer error-free data.
Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital
links and of systems with high noise level environments. An interesting characteristics of the clock and data recov-
ery (CDR) portion of the ispXPGA SERDES receiver is its ability to
fi
lter incoming signal jitter that is below the
clock recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming
data error free, with eye openings signi
fi
cantly less than that shown in Figure 23.
sysHSI Block AC Speci
fi
cations
Operating Frequency Ranges
Symbol
Description
Mode
Test Condition
Min
Max
Unit
f
CLK
REFCLK, SS_CLKIN,
SS_CLKOUT
All
40
250
MHz
f
SIN
Serial Input
SS: no CAL
with eo
SIN
with eo
SIN
with eo
SIN
with eo
SIN
400
750
1
800
1
850
1
850
1
Mbps
SS: CAL
400
Mbps
10B12B
400
Mbps
8B10B
400
Mbps
f
SOUT
1. These max. numbers apply to the -4 speed grade only. For the -3 speed grade, the corresponding numbers are:
SS: no CAL 650
SS: CAL
700
10B12B
800
8B10B
800
Serial Out
LVDS
C
L
=5 pF, R
L
=100 Ohm
400
850
Mbps
EO
SIN
V
LVDT
= 200mV
JT
TH
BIT TIME
JT
TH
: Optimum Threshold Crossing Jitter
1.2 V
JT
TH
相關(guān)PDF資料
PDF描述
LFX500C-4F900I The ispXPGA architecture
LFX1200C-03F900C Circular Connector; MIL SPEC:MIL-C-26482, Series I; Body Material:Aluminum Alloy; Series:MS3112; No. of Contacts:19; Connector Shell Size:14; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No
LFX1200C-03F900I The ispXPGA architecture
LFX1200C-04F900C The ispXPGA architecture
LFX500C-3F900C Circular Connector; No. of Contacts:26; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:16-26 RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFX200C-3FE680C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
LFX200C-3FE680I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
LFX200C-3FH516C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
LFX200C-3FH516I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
LFX200C-3FN256C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ispXPGA Family
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