參數(shù)資料
型號(hào)： LFX200B-4F900I
廠商： Lattice Semiconductor Corporation
英文描述： The ispXPGA architecture
中文描述： 在ispXPGA架構(gòu)
文件頁數(shù)： 19/89頁
文件大?。?/td> 941K
代理商： LFX200B-4F900I
Lattice Semiconductor
ispXPGA Family Data Sheet
19
Table 7. sysHSI Block REFCLK Selections
1
Con
fi
guration and Programming
The ispXPGA family of devices takes a unique approach to FPGA con
fi
guration memory. It contains two types of
memory, Static RAM and non-volatile E
2
CMOS cells. The static RAM is used to control the functionality of the
device during normal operation and the E
2
CMOS memory cells are used to load the SRAM. The E
2
CMOS memory
module can be thought of as the hard drive for the ispXPGA con
fi
guration and the SRAM as the working con
fi
gura-
tion memory. There is a one-to-one relationship between SRAM memory and the E
2
CMOS cells. The SRAM can be
con
fi
gured either from the E
2
CMOS memory or from an external source, as shown in Figure 21.
Figure 21 shows the different ports and modes that are used in the con
fi
guration and programming of the ispXPGA
devices. There are two possible ports that can be used for con
fi
guration of the SRAM memory: the ISP port which
is compliant to the IEEE 1149.1 Test Access Port (TAP) Std. and the ISP port which accommodates bit-wide con
fi
g-
uration. The sysCONFIG port allows byte-wide con
fi
guration of the SRAM con
fi
guration memory. When program-
ming the E
2
CMOS memory, only the 1149.1 TAP can be used.
Con
fi
guration and programming done through the 1149.1 Test Access Port (TAP) are fully compliant to both the
IEEE Std. 1149.1 Boundary Scan TAP speci
fi
cation and the IEEE Std. 1532 In-System Con
fi
guration speci
fi
cation.
To con
fi
gure or program the device using the 1149.1 TAP the device must be in the ISP mode. To con
fi
gure the
SRAM memory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the
device’s SRAM memory can be con
fi
gured either from the E
2
CMOS memory or from an external source through
the sysCONFIG mode. Additionally, the SRAM can be re-con
fi
gured from the E
2
CMOS memory by executing a
“REFRESH.” See Lattice technical note number TN1026,
ispXP Configuration Usage Guide,
for more in depth
information on the different programming modes, timing and wake-up, available at www.latticesemi.com.
sysHSI Block
Available Global Clock Nets
0
CLK0, CLK1, CLK2, CLK3
1
CLK0, CLK1, CLK2, CLK4
2
CLK0, CLK1, CLK2, CLK5
3
CLK0, CLK1, CLK3, CLK6
4
CLK0, CLK1, CLK3, CLK7
5
CLK0, CLK3, CLK5, CLK7
6
CLK0, CLK2, CLK5, CLK7
7
CLK0, CLK1, CLK5, CLK6
8
CLK0, CLK5, CLK6
9
CLK0, CLK5, CLK6, CLK7
1. Table 6 applies to all devices. Ignore sysHSI blocks not available
in a speci
fi
c device.
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