參數(shù)資料
型號(hào)： LFX200B-4F900I
廠商： Lattice Semiconductor Corporation
英文描述： The ispXPGA architecture
中文描述： 在ispXPGA架構(gòu)
文件頁數(shù)： 16/89頁
文件大?。?/td> 941K
代理商： LFX200B-4F900I
Lattice Semiconductor
ispXPGA Family Data Sheet
16
The second type of interface implemented is the terminated, single-ended interface standard. This group of inter-
faces includes different versions of SSTL and HSTL interfaces along with CTT, and GTL+. Usage of these particu-
lar I/O interfaces requires an additional V
REF
signal. At the system level a termination voltage, V
Typically an output will be terminated to V
TT
at the receiving end of the transmission line it is driving.
TT
, is also required.
The third type of interface standards are the differential standards LVDS, BLVDS, and LVPECL. The differential
standards require two I/O pins to create the differential pair. The logic level is determined by the difference in the
two signals. Table 6 lists how these interface standards are implemented in the ispXPGA devices.
For more information on sysIO capability, refer to Lattice technical note number TN1000,
for Lattice Devices
available at www.latticesemi.com.
sysIO Usage Guidelines
Figure 19. sysIO Banks per Device
Table 4. Number of I/Os per Bank
Device
Max. Number of I/Os per Bank (N)
XPGA 1200
62
XPGA 500
42
XPGA 200
26
XPGA 125
22
GND
V
CCO0
V
REF0
GND
V
CCO1
V
REF1
GND
V
CCO5
V
REF5
GND
V
CCO4
V
REF4
G
V
C
V
R
G
V
C
V
R
G
V
C
V
R
G
I
I
I/O 0
I/O 0
I/O N
I/O N
I/O N
I/O N
I/O 0
I/O 0
I
I
I
I
I
I
V
C
V
R
Bank 3
Bank 2
Bank 6
Bank 7
B
B
B
B
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