參數(shù)資料
型號(hào): LFX200B-3F900C
廠商: Lattice Semiconductor Corporation
英文描述: The ispXPGA architecture
中文描述: 在ispXPGA架構(gòu)
文件頁(yè)數(shù): 8/89頁(yè)
文件大?。?/td> 941K
代理商: LFX200B-3F900C
Lattice Semiconductor
ispXPGA Family Data Sheet
8
Figure 6. ispXPGA Wide Logic Generator
Con
fi
gurable Sequential Element
There are two registers in each CSE for a total of eight registers in each PFU. This high register count assists in
implementing ef
fi
cient pipelined applications with no utilization penalty. Each register can be con
fi
gured as a latch
or D type
fl
ip-
fl
op with either synchronous or asynchronous set or reset. Figure 2 shows the signals that feed the
register’s D inputs. Feed-through signals in the architecture ensure that registers are ef
fi
ciently utilized even if the
accompanying LUT is occupied.
Control Logic
The control signals available to the registers in a PFU are Clock, Clock Enable, and Set/Reset. Figure 7 shows the
various options available to generate the clock signal. As can be seen, the clock signal is the output of a 12:1 MUX
with true and compliment versions available from the 12:1 MUX. Each CSE can chose whether it uses the true or
compliment form of the clock. Figure 8 shows the Set/Reset selection for each PFU in the ispXPGA. A common
4B
XIN2
XIN3
S2
SEL1
4C
SEL2
S1
4D
S0
COUT
WIN2
WIN3
WLGW0
WLGW1
WLGX0
WLGX1
WLGY0
WLGY1
WLGZ0
WLGZ1
4A
S3
SEL0
YIN2
YIN3
ZIN2
ZIN3
SEL3
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參數(shù)描述
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LFX200B-3FE680C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
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