參數(shù)資料
型號： LFECP6E-3T144C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： LatticeECP/EC Family Data Sheet
中文描述： FPGA, 768 CLBS, 6100 GATES, 420 MHz, PQFP144
封裝： 20 X 20 MM, TQFP-144
文件頁數(shù)： 19/117頁
文件大?。?/td> 557K
代理商： LFECP6E-3T144C
2-16
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-18 shows the MULT sysDSP element.
Figure 2-18. MULT sysDSP Element
MAC sysDSP Element
In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. A registered over
fl
ow
signal is also available. The over
fl
ow conditions are provided later in this document. Figure 2-19 shows the MAC
sysDSP element.
Figure 2-19. MAC sysDSP Element
Multiplier
x
n
m
m
n
m
n
m
n
n
m
m+n
m+n
(default)
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Pipeline
Register
Input
Register
Multiplier
Multiplicand
Signed
Shift Register A In
Shift Register B In
Shift Register A Out
Shift Register B Out
Output
Input Data
Register A
Input Data
Register B
O
R
To
Multiplier
Multiplier
x
n
m
m+n
(default)
m+n+16 bits
(default)
m+n+16 bits
(default)
Input Data
Register B
Input Data
Register A
m
n
n
n
m
n
n
m
O
R
O
R
Accumulator
Multiplier
Multiplicand
SignedAB
Shift Register A In
Shift Register B In
Shift Register A Out
Shift Register B Out
Output
Addn
Accumsload
Pipeline
Register
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
To
Accumulator
To
Accumulator
To
Accumulator
Overflow
signal
相關(guān)PDF資料
PDF描述
LFECP6E-3T144I LatticeECP/EC Family Data Sheet
LFECP6E-4F256C Quad Low-Power Low-Voltage Operational Amplifier 14-SOIC
LFECP6E-4F256I LatticeECP/EC Family Data Sheet
LFECP6E-4F484C LatticeECP/EC Family Data Sheet
LFECP6E-4F484I LatticeECP/EC Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFECP6E-3T144I 功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 97 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP6E-3TN100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-3TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-3TN144C 功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 97 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP6E-3TN144I 功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 97 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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