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參數(shù)資料
| 型號(hào)： | LFECP6E-3T100I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | LatticeECP / EC的系列數(shù)據(jù)手冊(cè) |
| 文件頁(yè)數(shù)： | 26/117頁(yè) |
| 文件大?。?/td> | 557K |
| 代理商： | LFECP6E-3T100I |
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2-23
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-25 shows the diagram of the input register block.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal
fi
rst
passes through an optional delay block. This delay, if selected, reduces input-register hold-time requirement when
using a global clock.
The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Figure 2-26 shows the input register waveforms for DDR operation and Figure 2-27 shows the design tool primi-
tives. The SDR/SYNC registers have reset and clock enable available.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,
see the DDR Memory section of this data sheet.
Figure 2-25. Input Register Diagram
D
Q
D
Q
D
Q
D-Type
Fixed Delay
To Routing
DI
(From sysIO
Buffer)
DQS Delayed
(From DQS
Bus)
CLK0
(From Routing)
DDRCLKPOL
(From DDR
Polarity Control Bus)
INCK
INDD
Delay Block
DDR Registers
D-Type
D-Type
D
D-Type
Q
D
D-Type
/LATCH
Q
/LATCH
IPOS0
IPOS1
SDR & Sync
Registers
D0
D2
D1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFECP6E-3T144C | LatticeECP/EC Family Data Sheet |
| LFECP6E-3T144I | LatticeECP/EC Family Data Sheet |
| LFECP6E-4F256C | Quad Low-Power Low-Voltage Operational Amplifier 14-SOIC |
| LFECP6E-4F256I | LatticeECP/EC Family Data Sheet |
| LFECP6E-4F484C | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFECP6E-3T144C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6.1 LUT 97 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFECP6E-3T144I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6.1 LUT 97 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFECP6E-3TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP6E-3TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP6E-3TN144C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6.1 LUT 97 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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