參數(shù)資料
型號： LFECP40E-5T144C
廠商： Lattice Semiconductor Corporation
英文描述： LatticeECP/EC Family Data Sheet
中文描述： LatticeECP / EC的系列數(shù)據(jù)手冊
文件頁數(shù)： 59/117頁
文件大?。?/td> 557K
代理商： LFECP40E-5T144C
3-23
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC sysCONFIG Port Timing Speci
fi
cations
Over Recommended Operating Conditions
Parameter
sysCONFIG Byte Data Flow
t
SUCBDI
Byte D[0:7] Setup Time to CCLK
t
HCBDI
Byte D[0:7] Hold Time to CCLK
t
CODO
Clock to Dout in Flowthrough Mode
t
SUCS
CS[0:1] Setup Time to CCLK
t
HCS
CS[0:1] Hold Time to CCLK
t
SUWD
Write Signal Setup Time to CCLK
t
HWD
Write Signal Hold Time to CCLK
t
DCB
CCLK to BUSY Delay Time
t
CORD
Clock to out for read Data
sysCONFIG Byte Slave Clocking
t
BSCH
Byte Slave Clock Minimum High Pulse
t
BSCL
Byte Slave Clock Minimum Low Pulse
t
BSCYC
Byte Slave Clock Cycle Time
sysCONFIG Serial (Bit) Data Flow
t
SUSCDI
Din Setup Time to CCLK Slave Mode
t
HSCDI
Din Hold Time to CCLK Slave Mode
t
CODO
Clock to Dout in Flowthrough Mode
t
SUMCDI
Din Setup Time to CCLK Master Mode
t
HMCDI
Din Hold Time to CCLK Master Mode
sysCONFIG Serial Slave Clocking
t
SSCH
Serial Slave Clock Minimum High Pulse
t
SSCL
Serial Slave Clock Minimum Low Pulse
sysCONFIG POR, Initialization and Wake Up
t
ICFG
Minimum Vcc to INIT High
t
VMC
Time from t
ICFG
to valid Master Clock
t
PRGMRJ
PROGRAMB Pin Pulse Rejection
t
PRGM
PROGRAMB Low Time to Start Con
fi
guration
t
DINIT
PROGRAMB High to INIT High Delay
t
DPPINIT
Delay Time from PROGRAMB Low to INIT Low
t
DPPDONE
Delay Time from PROGRAMB Low to DONE Low
t
IODISS
User I/O Disable from PROGRAMB Low
t
IOENSS
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
t
MWC
Additional Wake Master Clock Signals after Done Pin High
sysCONFIG SPI Port
t
CFGX
Init High to CCLK Low
t
CSSPI
Init High to CSSPIN Low
t
CSCCLK
CCLK Low before CSSPIN Low
t
SOCDO
CCLK Low to Output Valid
t
SOE
CSSPIN Active Setup Time
t
CSPID
CSSPIN Low to First Clock Edge Setup Time
f
MAXSPI
Max Frequency for SPI
Description
Min
Max
Units
7
1
—
7
1
7
1
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
TBD
—
—
—
—
12
12
6
6
15
—
—
—
ns
ns
ns
7
1
—
7
1
—
—
12
—
—
ns
ns
ns
ns
ns
6
6
—
—
ns
ns
—
—
—
25
—
—
—
—
—
120
50
2
10
—
1
37
37
25
25
—
ms
us
ns
ns
ms
ns
ns
ns
ns
cycles
—
—
0
—
300
1
2
-
15
—
μs
us
ns
ns
ns
ns
MHz
300+3cyc
—
600+6cyc
20
相關(guān)PDF資料
PDF描述
LFECP40E-5T144I Dual Low-Power Low-Voltage Operational Amplifier 8-PDIP 0 to 70
LFECP6E-3F256C LatticeECP/EC Family Data Sheet
LFECP6E-3F256I LatticeECP/EC Family Data Sheet
LFECP6E-3F484I LinCMOS Dual Operational Amplifier 8-SOIC
LFECP6E-3F900I LatticeECP/EC Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFECP40E-5T144I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-3F256C 功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 195 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP6E-3F256I 功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 195 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP6E-3F484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 6.1 LUT 224 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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