參數(shù)資料
型號(hào)： LFECP40E-5T144C
廠商： Lattice Semiconductor Corporation
英文描述： LatticeECP/EC Family Data Sheet
中文描述： LatticeECP / EC的系列數(shù)據(jù)手冊(cè)
文件頁數(shù)： 14/117頁
文件大?。?/td> 557K
代理商： LFECP40E-5T144C
2-11
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Table 2-5. PLL Signal Descriptions
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-13 illustrates
the DCS Block Macro.
Figure 2-13. DCS Block Primitive
Figure 2-14 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
Signal
I/O
I
I
I
O
O
O
O
I
I
I
I
O
O
O
Description
CLKI
CLKFB
RST
CLKOS
CLKOP
CLKOK
LOCK
DDAMODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
Clock input from external pin or routing
PLL feedback input from CLKOP, clocknet, or external pin
“1” to reset PLL
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (No phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag
Dynamic Delay Input
Dynamic Delay Zero Output
Dynamic Delay Lag/Lead Output
Dynamic Delay Output
DCS
CLK0
DCSOUT
CLK1
SEL
相關(guān)PDF資料
PDF描述
LFECP40E-5T144I Dual Low-Power Low-Voltage Operational Amplifier 8-PDIP 0 to 70
LFECP6E-3F256C LatticeECP/EC Family Data Sheet
LFECP6E-3F256I LatticeECP/EC Family Data Sheet
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFECP40E-5T144I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP6E-3F256C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6.1 LUT 195 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP6E-3F256I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6.1 LUT 195 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP6E-3F484C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6.1 LUT 224 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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