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參數(shù)資料
| 型號： | LFECP20E-3F256C |
| 廠商： | Lattice Semiconductor Corporation |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | LinCMOS(TM) Quad Operational Amplifier 14-SOIC |
| 中文描述： | LatticeECP / EC的系列數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 31/117頁 |
| 文件大小： | 557K |
| 代理商： | LFECP20E-3F256C |
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2-28
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Polarity Control Logic
In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system Clock (during the READ cycle) is unknown.
The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup
and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
sysIO Buffer
Each I/O is associated with a
fl
exible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in eight groups referred to as Banks. The sysIO buffers allow users to implement the wide
variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeECP/EC devices have eight sysIO buffer banks; each is capable of supporting multiple I/O standards. Each
sysIO bank has its own I/O supply voltage (V
CCIO
), and two voltage references V
REF1
and V
REF2
resources allow-
ing each bank to be completely independent from each other. Figure 2-33 shows the eight banks and their associ-
ated supplies.
In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-
X) are powered using V
CCIO.
LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as
fi
xed threshold
input independent of V
CCIO.
In addition to the bank V
CCIO
supplies, the LatticeECP/EC devices have a V
CC
core logic
power supply, and a V
CCAUX
supply that power all differential and referenced buffers.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be con
fi
gured to be a
reference voltage supply pin. Each I/O is individually con
fi
gurable based on the bank’s supply and reference volt-
ages.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFECP20E-3F256I | LatticeECP/EC Family Data Sheet |
| LFECP20E-3F484C | LinCMOS(TM) Quad Operational Amplifier 14-PDIP |
| LFECP20E-3F484I | LatticeECP/EC Family Data Sheet |
| LFECP20E-3F672I | LinCMOS(TM) Quad Operational Amplifier 14-SOIC |
| LFECP20E-3F900I | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFECP20E-3F256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP20E-3F484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 360 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFECP20E-3F484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 360 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFECP20E-3F672C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFECP20E-3F672I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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