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參數(shù)資料
| 型號： | LFECP10E-5F484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | Quad Low-Voltage Operational Amplifier 14-SOIC 0 to 70 |
| 中文描述： | FPGA, 1280 CLBS, 10200 GATES, 420 MHz, PBGA484 |
| 封裝： | 23 X 23 MM, FPBGA-484 |
| 文件頁數(shù)： | 64/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFECP10E-5F484C |
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4-2
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
TDI
I
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for con
fi
guration by sending
appropriate command. (Note: once a con
fi
guration port is selected it is
locked. Another con
fi
guration port cannot be selected until the power-up
sequence). Pull-up is enabled during con
fi
guration.
Output pin. Test Data out pin used to shift data out of device using 1149.1.
V
CCJ
- The power supply pin for JTAG Test Access Port.
TDO
V
CCJ
Con
fi
guration Pads
(used during sysCONFIG)
O
—
CFG[2:0]
I
Mode pins used to specify con
fi
guration modes values latched on rising edge
of INITN. During con
fi
guration, a pull-up is enabled. These are dedicated
pins.
Open Drain pin. Indicates the FPGA is ready to be con
fi
gured. During con
fi
g-
uration, a pull-up is enabled. It is a dedicated pin.
Initiates con
fi
guration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
Open Drain pin. Indicates that the con
fi
guration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
Con
fi
guration Clock for con
fi
guring an FPGA in sysCONFIG mode.
Read control command in SPI3 or SPIX mode.
sysCONFIG chip select (Active low). During con
fi
guration, a pull-up is
enabled.
sysCONFIG chip select (Active low). During con
fi
guration, a pull-up is
enabled.
Write Data on Parallel port (Active low).
sysCONFIG Port Data I/O.
Output for serial con
fi
guration data (rising edge of CCLK) when using
sysCONFIG port.
Input for serial con
fi
guration data (clocked with CCLK) when using sysCON-
FIG port. During con
fi
guration, a pull-up is enabled.
INITN
I/O
PROGRAMN
I
DONE
I/O
CCLK
BUSY/SISPI
I/O
I/O
CSN
I
CS1N
I
WRITEN
D[7:0]/SPID[0:7]
I
I/O
DOUT/CSON
O
DI/CSSPIN
I
Signal Descriptions (Cont.)
Signal Name
I/O
Descriptions
相關PDF資料 |
PDF描述 |
|---|---|
| LFECP10E-5F484I | LatticeECP/EC Family Data Sheet |
| LFECP10E-5F672I | Quad Low-Voltage Operational Amplifier 14-PDIP 0 to 70 |
| LFECP10E-5F900I | LatticeECP/EC Family Data Sheet |
| LFECP15E-5F256I | LatticeECP/EC Family Data Sheet |
| LFECP15E-5F484C | 12-Bit 66 kSPS ADC Ser. Out, Pgrmable MSB/LSB First, Pgrmable Power Down/Output Data Length, 11 Ch. 20-PLCC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LFECP10E-5F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP10E-5F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP10E-5F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP10E-5F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP10E-5F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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