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參數(shù)資料
| 型號： | LFECP10E-5F484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | Quad Low-Voltage Operational Amplifier 14-SOIC 0 to 70 |
| 中文描述： | FPGA, 1280 CLBS, 10200 GATES, 420 MHz, PBGA484 |
| 封裝： | 23 X 23 MM, FPBGA-484 |
| 文件頁數(shù)： | 6/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFECP10E-5F484C |
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2-3
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
PFU and PFF Blocks
The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-3. PFU Diagram
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice.
The registers in the slice can be con
fi
gured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
D
FF/
Latch
D
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
From
Routing
To
Routing
Slice 3
LUT4 &
CARRY
LUT4 &
CARRY
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
相關PDF資料 |
PDF描述 |
|---|---|
| LFECP10E-5F484I | LatticeECP/EC Family Data Sheet |
| LFECP10E-5F672I | Quad Low-Voltage Operational Amplifier 14-PDIP 0 to 70 |
| LFECP10E-5F900I | LatticeECP/EC Family Data Sheet |
| LFECP15E-5F256I | LatticeECP/EC Family Data Sheet |
| LFECP15E-5F484C | 12-Bit 66 kSPS ADC Ser. Out, Pgrmable MSB/LSB First, Pgrmable Power Down/Output Data Length, 11 Ch. 20-PLCC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LFECP10E-5F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP10E-5F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP10E-5F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP10E-5F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFECP10E-5F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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