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| 型號(hào)： | LFEC3E-5TN100C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 87/163頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.1KLUTS 67I/O 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | EC |
| 邏輯元件/單元數(shù)： | 3100 |
| RAM 位總計(jì)： | 56320 |
| 輸入/輸出數(shù)： | 67 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
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1-2
Introduction
LatticeECP/EC Family Data Sheet
Introduction
The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For
maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an efficient FPGA
fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-
DSP (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC
(EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function
blocks to achieve lower cost solutions.
The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical
FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.
Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prev-
alent in cost-sensitive applications.
The ispLEVER
design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP/EC FPGA family. Synthesis library support for LatticeECP/EC is available for popular logic synthesis
tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to
place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE modules for the LatticeECP/EC
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
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| EMC50DRXN-S734 | CONN EDGECARD 100PS DIP .100 SLD |
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| EMC50DRXH-S734 | CONN EDGECARD 100PS DIP .100 SLD |
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| LFEC3E-5QN208C | IC FPGA 3.1KLUTS 145I/O 208-PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC3E-5TN100I | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC3E-5TN144C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 3.1K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC3E-5TN144I | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F256C | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC40E-3F256I | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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