參數(shù)資料
型號： LFEC3E-5T144C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： LatticeECP/EC Family Data Sheet
中文描述： FPGA, 384 CLBS, 3100 GATES, 420 MHz, PQFP144
封裝： 20 X 20 MM, TQFP-144
文件頁數(shù)： 12/117頁
文件大?。?/td> 557K
代理商： LFEC3E-5T144C
2-9
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-8. Per Quadrant Primary Clock Selection
Figure 2-9. Per Quadrant Secondary Clock Selection
Figure 2-10. Slice Clock Selection
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nal to the feedback divider: from the CLKOP, from the clock net, or from an external pin. There is a PLL_LOCK sig-
nal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
grammed during con
fi
guration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing
1
DCS
DCS
1. Smaller devices have fewer PLL related lines.
4 Secondary Clocks per Quadrant
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
Primary Clock
Secondary Clock
Routing
Clock to Slice
GND
4
3
相關PDF資料
PDF描述
LFEC3E-5T144I LatticeECP/EC Family Data Sheet
LFEC40E-3F256C LatticeECP/EC Family Data Sheet
LFEC40E-3F256I LatticeECP/EC Family Data Sheet
LFEC40E-3F484C LatticeECP/EC Family Data Sheet
LFEC40E-3F484I LatticeECP/EC Family Data Sheet
相關代理商/技術參數(shù)
參數(shù)描述
LFEC3E-5T144CES 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 97 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-5T144I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC3E-5TN100C 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-5TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC3E-5TN144C 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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