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參數(shù)資料
| 型號： | LFEC3E-3T100I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | STANDOFF RND 4-40THR .625L BRS |
| 中文描述： | FPGA, 384 CLBS, 3100 GATES, 420 MHz, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 35/117頁 |
| 文件大小： | 557K |
| 代理商： | LFEC3E-3T100I |
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2-32
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Con
fi
guration and Testing
The following section describes the con
fi
guration and testing features of the LatticeECP/EC family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test
access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veri
fi
cation. The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
V
CCJ
and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Con
fi
guration
All LatticeECP/EC devices contain two possible ports that can be used for device con
fi
guration. The test access
port (TAP), which supports bit-wide con
fi
guration, and the sysCONFIG port that supports both byte-wide and serial
con
fi
guration.
The TAP supports both the IEEE Std. 1149.1 Boundary Scan speci
fi
cation and the IEEE Std. 1532 In-System Con-
fi
guration speci
fi
cation. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and
the rest being dual-use pins. When sysCONFIG mode is not used, these dual-use pins are available for general
purpose I/O. There are four con
fi
guration options for LatticeECP/EC devices:
1.
Industry standard SPI memories.
2.
Industry standard byte wide
fl
ash and ispMACH 4000 for control/addressing.
3.
Con
fi
guration from system microprocessor via the con
fi
guration bus or TAP.
4.
Industry standard FPGA board memory.
On power-up, the FPGA SRAM is ready to be con
fi
gured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a
con
fi
guration port is selected, that port is locked and another con
fi
guration port cannot be activated until the next
power-up sequence.
For more information on device con
fi
guration, please see details of additional technical documentation at the end
of this data sheet.
Internal Logic Analyzer Capability (ispTRACY)
All LatticeECP/EC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide
capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace
memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at com-
pile time.
For more information on ispTRACY, please see information regarding additional technical documentation at the
end of this data sheet.
External Resistor
LatticeECP/EC devices require a single external, 10K ohm +/- 1% value between the XRES pin and ground.
Device con
fi
guration will not be completed if this resistor is missing. There is no boundary scan register on the
external resistor pad.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFEC3E-3T144C | LatticeECP/EC Family Data Sheet |
| LFEC3E-3T144I | LatticeECP/EC Family Data Sheet |
| LFEC3E-4F256C | LatticeECP/EC Family Data Sheet |
| LFEC3E-4F256I | LatticeECP/EC Family Data Sheet |
| LFEC3E-4F484C | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC3E-3T100IES | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 67 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC3E-3T144C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC3E-3T144CES | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 97 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC3E-3T144I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 97 IO 1.2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC3E-3T144IES | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 97 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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