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參數(shù)資料
| 型號(hào)： | LFEC20E-4F672C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | FPGA, 2464 CLBS, 19700 GATES, 420 MHz, PBGA672 |
| 封裝： | 27 X 27 MM, FPBGA-672 |
| 文件頁數(shù)： | 36/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFEC20E-4F672C |
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2-33
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Oscillator
Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master serial clock for con-
fi
guration. The oscillator and the master serial clock run continuously. The default value of the master serial clock is
2.5MHz. Table 2-15 lists all the available Master Serial Clock frequencies. When a different Master Serial Clock is
selected during the design process, the following sequence takes place:
1.
User selects a different Master Serial Clock frequency.
2.
During con
fi
guration the device starts with the default (2.5MHz) Master Serial Clock frequency.
3.
The clock con
fi
guration settings are contained in the early con
fi
guration bit stream.
4.
The Master Serial Clock frequency changes to the selected frequency once the clock con
fi
guration bits are
received.
For further information on the use of this oscillator for con
fi
guration, please see details of additional technical docu-
mentation at the end of this data sheet.
Table 2-15. Selectable Master Serial Clock (CCLK) Frequencies During Configuration
Density Shifting
The LatticeECP/EC family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design
targeted for a high-density device to a lower density device. However, the exact details of the
fi
nal resource utiliza-
tion will impact the likely success in each case.
CCLK (MHz)
2.5*
4.3
5.4
6.9
8.1
9.2
10.0
CCLK (MHz)
13
15
20
26
30
34
41
CCLK (MHz)
45
51
55
60
130
—
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFEC20E-4F672I | LatticeECP/EC Family Data Sheet |
| LFEC20E-4F900I | LatticeECP/EC Family Data Sheet |
| LFEC20E-4T100I | LatticeECP/EC Family Data Sheet |
| LFEC20E-4T144C | LatticeECP/EC Family Data Sheet |
| LFEC20E-4T144I | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC20E-4F672I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC20E-4F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-4F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-4FN256C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-4FN256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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