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參數(shù)資料
| 型號： | LFEC20E-4F672C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | LatticeECP/EC Family Data Sheet |
| 中文描述： | FPGA, 2464 CLBS, 19700 GATES, 420 MHz, PBGA672 |
| 封裝： | 27 X 27 MM, FPBGA-672 |
| 文件頁數(shù)： | 16/117頁 |
| 文件大?。?/td> | 557K |
| 代理商： | LFEC20E-4F672C |
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2-13
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on speci
fi
c design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-15 shows the four basic memory con
fi
gurations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
Figure 2-15. sysMEM EBR Primitives
The EBR memory supports three forms of write behavior for single port or dual port operation:
1.
Normal
address) does not appear on the output.
– data on the output appears only during read cycle. During a write cycle, the data (at the current
2.
Write Through
– a copy of the input data appears at the output of the same port, during a write cycle.
3.
Read-Before-Write
– when new data is being written, the old content of the address appears at the output.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated
resets for both ports are as shown in Figure 2-16.
EBR
AD[12:0]
DI[35:0]
CLK
CE
RST
WE
CS[2:0]
DO[35:0]
Single Port RAM
EBR
True Dual Port RAM
Pseudo-Dual Port RAM
ROM
AD[12:0]
CLK
CE
RST
DO[35:0]
CS[2:0]
EBR
EBR
ADA[12:0]
DIA[17:0]
CLKA
CEA
RSTA
WEA
CSA[2:0]
DOA[17:0]
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
ADW[12:0]
DI[35:0]
CLKW
CEW
WE
RST
CS[2:0]
ADR[12:0]
DO[35:0]
CER
CLKR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFEC20E-4F672I | LatticeECP/EC Family Data Sheet |
| LFEC20E-4F900I | LatticeECP/EC Family Data Sheet |
| LFEC20E-4T100I | LatticeECP/EC Family Data Sheet |
| LFEC20E-4T144C | LatticeECP/EC Family Data Sheet |
| LFEC20E-4T144I | LatticeECP/EC Family Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC20E-4F672I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC20E-4F900C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-4F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-4FN256C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-4FN256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
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