參數(shù)資料
型號： LFEC20E-3F672C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： LatticeECP/EC Family Data Sheet
中文描述： FPGA, 2464 CLBS, 19700 GATES, 420 MHz, PBGA672
封裝： 27 X 27 MM, FPBGA-672
文件頁數(shù)： 57/117頁
文件大?。?/td> 557K
代理商： LFEC20E-3F672C
3-21
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
HSTL15_I
HSTL15_II
HSTL15_III
HSTL15D_I
HSTL15D_III
SSTL33_I
SSTL33_II
SSTL33D_I
SSTL33D_II
SSTL25_I
SSTL25_II
SSTL25D_I
SSTL25D_II
SSTL18_I
SSTL18D_I
LVTTL33_4mA
LVTTL33_8mA
LVTTL33_12mA
LVTTL33_16mA
LVTTL33_20mA
LVCMOS33_4mA
LVCMOS33_8mA
LVCMOS33_12mA
LVCMOS33_16mA
LVCMOS33_20mA
LVCMOS25_4mA
LVCMOS25_8mA
LVCMOS25_12mA
LVCMOS25_16mA
LVCMOS25_20mA
LVCMOS18_4mA
LVCMOS18_8mA
LVCMOS18_12mA
LVCMOS18_16mA
LVCMOS15_4mA
LVCMOS15_8mA
LVCMOS12_2mA
LVCMOS12_6mA
LVCMOS12_4mA
PCI33
1. Timing adders are characterized but not tested on every device.
2. LVCMOS timing measured with the load speci
fi
ed in Switching Test Conditions table.
3. All other standards according to the appropriate speci
fi
cation.
Rev F 0.17
HSTL_15 class I
HSTL_15 class II
HSTL_15 class III
Differential HSTL 15 class I
Differential HSTL 15 class III
SSTL_3 class I
SSTL_3 class II
Differential SSTL_3 class I
Differential SSTL_3 class II
SSTL_2 class I
SSTL_2 class II
Differential SSTL_2 class I
Differential SSTL_2 class II
SSTL_1.8 class I
Differential SSTL_1.8 class I
LVTTL 4mA drive
LVTTL 8mA drive
LVTTL 12mA drive
LVTTL 16mA drive
LVTTL 20mA drive
LVCMOS 3.3 4mA drive
LVCMOS 3.3 8mA drive
LVCMOS 3.3 12mA drive
LVCMOS 3.3 16mA drive
LVCMOS 3.3 20mA drive
LVCMOS 2.5 4mA drive
LVCMOS 2.5 8mA drive
LVCMOS 2.5 12mA drive
LVCMOS 2.5 16mA drive
LVCMOS 2.5 20mA drive
LVCMOS 1.8 4mA drive
LVCMOS 1.8 8mA drive
LVCMOS 1.8 12mA drive
LVCMOS 1.8 16mA drive
LVCMOS 1.5 4mA drive
LVCMOS 1.5 8mA drive
LVCMOS 1.2 2mA drive
LVCMOS 1.2 6mA drive
LVCMOS 1.2 4mA drive
PCI33
-0.07
0.00
-0.05
-0.07
-0.05
-0.20
0.25
-0.20
0.25
-0.10
0.10
-0.10
0.10
-0.14
-0.14
-0.06
-0.05
-0.06
-0.05
-0.07
-0.06
-0.05
-0.06
-0.05
-0.07
0.04
0.03
0.00
0.03
-0.05
0.07
0.07
0.06
0.07
0.12
0.11
0.22
0.21
0.22
2.00
-0.08
0.00
-0.06
-0.08
-0.06
-0.24
0.30
-0.24
0.30
-0.11
0.12
-0.11
0.12
-0.17
-0.17
-0.07
-0.07
-0.07
-0.07
-0.09
-0.07
-0.07
-0.07
-0.07
-0.09
0.05
0.03
0.00
0.03
-0.06
0.08
0.08
0.07
0.08
0.14
0.13
0.26
0.25
0.26
2.40
-0.09
0.00
-0.07
-0.09
-0.07
-0.28
0.35
-0.28
0.35
-0.13
0.14
-0.13
0.14
-0.20
-0.20
-0.09
-0.08
-0.08
-0.08
-0.10
-0.09
-0.08
-0.08
-0.08
-0.10
0.05
0.04
0.00
0.04
-0.07
0.10
0.09
0.09
0.09
0.16
0.15
0.31
0.29
0.31
2.80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LatticeECP/EC Family Timing Adders
1, 2, 3
(Continued)
Over Recommended Operating Conditions
Buffer Type
Description
-5
-4
-3
Units
相關(guān)PDF資料
PDF描述
LFECP20E-3F672C LatticeECP/EC Family Data Sheet
LFEC40E-3F672C LatticeECP/EC Family Data Sheet
LFECP40E-3F672C LatticeECP/EC Family Data Sheet
LFEC1E-3F672I LatticeECP/EC Family Data Sheet
LFECP1E-3F672I LatticeECP/EC Family Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC20E-3F672CAU1 制造商:Lattice Semiconductor 功能描述:LFEC20E-3F672CAU1
LFEC20E-3F672I 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC20E-3F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-3F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-3FN256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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