參數(shù)資料
型號： LFEC20E-3F672C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： LatticeECP/EC Family Data Sheet
中文描述： FPGA, 2464 CLBS, 19700 GATES, 420 MHz, PBGA672
封裝： 27 X 27 MM, FPBGA-672
文件頁數(shù)： 22/117頁
文件大?。?/td> 557K
代理商： LFEC20E-3F672C
2-19
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Table 2-8. An Example of Sign Extension
OVERFLOW Flag from MAC
The sysDSP block provides an over
fl
ow output to indicate that the accumulator has over
fl
owed. When two
unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and
over
fl
ow signal is indicated. When two positive numbers are added with a negative sum and when two negative
numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an over
fl
ow
signal is indicated. Note when over
fl
ow occurs the over
fl
ow
fl
ag is present for only one cycle. By counting these
over
fl
ow pulses in FPGA logic, larger accumulators can be constructed. The conditions over
fl
ow signal for signed
and unsigned operands are listed in Figure 2-22.
Figure 2-22. Accumulator Overflow/Underflow Conditions
ispLEVER Module Manager
The user can access the sysDSP block via the ispLEVER Module Manager, which has options to con
fi
gure each
DSP module (or group of modules) or through direct HDL instantiation. Additionally Lattice has partnered Math-
works to support instantiation in the Simulink tool, which is a Graphical Simulation Environment. Simulink works
with ispLEVER and dramatically shortens the DSP design cycle in Lattice FPGAs.
Number Unsigned
+5
-6
Unsigned
9-bit
000000101
000000110
Unsigned
18-bit
Signed
0101
1010
Two’s Complement
Signed 9-Bits
000000101
111111010
Two’s Complement
Signed 18-bits
000000000000000101
111111111111111010
0101
0110
000000000000000101
000000000000000110
000000000
111111111
000000001
000000010
000000011
111111101
111111110
Overflow signal is generated
for one cycle when this
boundary is crossed
0
+1
+2
+3
-3
-2
-1
Unsigned Operation
Signed Operation
0101111111
0101111110
0101111101
0101111100
1010000010
1010000001
1010000000
255
254
253
252
254
255
256
000000000
000000001
000000010
000000011
111111101
111111110
111111111
Carry signal is generated for
one cycle when this
boundary is crossed
0
1
2
3
509
510
511
0101111111
1010000000
0101111110
0101111101
0101111100
1010000010
1010000001
255
256
254
253
252
258
257
相關PDF資料
PDF描述
LFECP20E-3F672C LatticeECP/EC Family Data Sheet
LFEC40E-3F672C LatticeECP/EC Family Data Sheet
LFECP40E-3F672C LatticeECP/EC Family Data Sheet
LFEC1E-3F672I LatticeECP/EC Family Data Sheet
LFECP1E-3F672I LatticeECP/EC Family Data Sheet
相關代理商/技術參數(shù)
參數(shù)描述
LFEC20E-3F672CAU1 制造商:Lattice Semiconductor 功能描述:LFEC20E-3F672CAU1
LFEC20E-3F672I 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC20E-3F900C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-3F900I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-3FN256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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