參數(shù)資料
型號(hào): LFEC1E-4T100C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: LatticeECP/EC Family Data Sheet
中文描述: FPGA, 192 CLBS, 1500 GATES, 420 MHz, PQFP100
封裝: 14 X 14 MM, TQFP-100
文件頁數(shù): 45/117頁
文件大?。?/td> 557K
代理商: LFEC1E-4T100C
3-9
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LVPECL
The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in
Figure 3-2 is one possible solution for point-to-point signals.
Figure 3-2. Differential LVPECL
Table 3-2. LVPECL DC Conditions
1
Over Recommended Operating Conditions
For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni-
cal information at the end of this data sheet.
Parameter
Z
OUT
R
P
R
T
V
OH
V
OL
V
OD
V
CM
Z
BACK
I
DC
1. For input buffer, see LVDS table.
Description
Typical
100
150
100
2.03
1.27
0.76
1.65
85.7
12.7
Units
ohm
ohm
ohm
V
V
V
V
ohm
mA
Output impedance
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
Output differential voltage
Output common mode voltage
Back impedance
DC output current
Transmission line, Zo = 100 ohm differential
100 ohms
100 ohms
100 ohms
Off-chip
3.3V
3.3V
+
-
~150 ohms
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