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參數(shù)資料
| 型號(hào)： | LF48410 |
| 廠商： | Logic Devices Incorporated |
| 英文描述： | 1024 x 24-bit Video Histogrammer |
| 中文描述： | 1024 × 24位視頻Histogrammer |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 302K |
| 代理商： | LF48410 |
DEVICES INCORPORATED
LF48410
1024 x 24-bit Video Histogrammer
4
Video Imaging Products
08/08/2000–LDS.48410-L
into the memory array at the address
defined by the counter. The value
already in the memory array at that
address is output on DIO
23-0
(if RD is
LOW). Every rising edge of CLK
causes the counter to increment its
output by one until the counter
reaches a value of 1023. At this point,
the counter will hold the value of
1023 and writing to the memory array
will be disabled. DIN
23-0
is delayed
internally three clock cycles to match
the latency of the address generator.
In Asynchronous 16/24 Mode, data is
loaded into the memory array as
detailed in the asynchronous mode
sections. If the Cumulative Distribu-
tion Function is the desired transfor-
mation function, the memory array
will contain this data as soon as the
Histogram Accumulate function has
been completed.
Once the memory array contains the
desired data, the device needs to be
put in Look Up Table Read Mode by
setting START HIGH. In Look Up
Table Read Mode, pixel values are
input on PIN
9-0
and are latched on
the rising edge of CLK. Data at the
address defined by PIN
9-0
is read out
of the memory array and output on
DIO
23-0
(if RD is LOW). If Look Up
Table Write Mode was used to load
the memory array, it is important to
wait until the third clock cycle after
START goes HIGH to input data on
PIN
9-0
to insure that all data is
written into the memory array before
any reading is done.
BIN ACCUMULATE MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure
4. PIN
9-0
provides address data for
the memory array and is latched on
the rising edge of CLK. Data at the
address defined by PIN
9-0
is read out
of the memory array and added to
the data on DIN
23-0
. This new value
is written back to the memory array,
in the same location where the last
read occured, and is also output on
DIO
23-0
(if RD is LOW). As long as
START is LOW, the device will be
enabled for Bin Accumulate Mode.
When START is HIGH, the device will
still read address values on PIN
9-0
, but
the addressed data will not be added
to anything. The unchanged data will
be output on DIO
23-0
and is not
written back to the memory array
(writing is disabled). START and
DIN
23-0
are delayed internally three
clock cycles to match the latency of
the address generator.
DELAY MEMORY MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure
5. This mode allows the device to
function as a row buffer. The internal
counter is used to generate address
data for the memory array. When
START goes LOW, the counter is
reset to zero. Delay length (row
length) is determined by reseting the
counter every N–4 clock cycles, where
N is the number of delays. For
F
IGURE
3.
L
OOK
U
P
T
ABLE
M
ODE
F
IGURE
4.
B
IN
A
CCUMULATE
M
ODE
CLK
ADDRESS
GENERATOR
CONTROL
START
I/F
DIO
23-0
24
RD
COUNTER
PIN
9-0
10
DIN
23-0
24
3
"0"
RAM ARRAY
DATA IN
DATA OUT
WR
ADDRESS
(TO ALL REGISTERS)
NOTE: NUMBER IN REGISTER INDICATES
NUMBER OF PIPELINE DELAYS.
PIN
9-0
CLK
TO ALL REGISTERS
10
RAM ARRAY
DATA IN
DATA OUT
ADDRESS
GADDRESS
CONTROL
START
"0"
DIO
I/F
DIO
23-0
24
RD
DIN
23-0
24
3
NOTE: NUMBER OF PIPELINE DELAYS.
WR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LF48410JC25 | 1024 x 24-bit Video Histogrammer |
| LF48410JC30 | 1024 x 24-bit Video Histogrammer |
| LF9502 | 2K Programmable Line Buffer(2K可編程線緩沖器) |
| LF9502JC20 | 2K Programmable Line Buffer |
| LF9502JC25 | 2K Programmable Line Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LF48410GC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Histogrammer |
| LF48410GC30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Histogrammer |
| LF48410GM30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Histogrammer |
| LF48410GM39 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Histogrammer |
| LF48410GMB30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Histogrammer |
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