參數(shù)資料
型號: LF3338QC12
廠商: LOGIC DEVICES INC
元件分類: 數(shù)字信號處理外設(shè)
英文描述: 8-Bit Vertical Digital Image Filter
中文描述: 8-BIT, DSP-DIGITAL FILTER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 4/15頁
文件大?。?/td> 303K
代理商: LF3338QC12
DEVICES INCORPORATED
LF3338
8-Bit Vertical Digital Image Filter
4
Video Imaging Products
04/06/1999–LDS.3338-B
ACC — Accumulator Control
When ACC is HIGH, the accumulator
is enabled for accumulation and the
accumulator output register is
disabled for loading. When ACC is
LOW, no accumulation is performed
and the accumulator output register
is enabled for loading. ACC is
latched on the rising edge of CLK.
SHEN — Shift Enable
SHEN enables or disables the
loading of data into the input/
cascade registers and the line
buffers. When SHEN is LOW, data
is loaded into the input/cascade
registers and shifted through the
line buffers on the rising edge of
CLK. When SHEN is HIGH, data
can not be loaded into the input/
cascade registers or shifted through
the line buffers and their contents
will not be changed.
RSL
3-0
— Round/Select/Limit Control
RSL
3-0
determines which of the
sixteen user-programmable round/
select/limit registers are used in the
round/select/limit circuitry. A
value of 0 on RSL
3-0
selects round/
select/limit register 0. A value of 1
selects round/select/limit register 1
and so on. RSL
3-0
is latched on the
rising edge of CLK (see the round,
select, and limit sections for a
complete discussion).
OED — DOUT Output Enable
When OED is LOW, DOUT
15-0
is
enabled for output. When OED is
HIGH, DOUT
15-0
is placed in a
high-impedance state.
OEC — COUT Output Enable
When OEC is LOW, COUT
7-0
is
enabled for output. When OEC is
HIGH, COUT
7-0
is placed in a high-
impedance state.
BITS
FUNCTION
DESCRIPTION
0
Limit Enable
0: Limiting Disabled
1: Limiting Enabled
11-1
Reserved
Must be set to “0”
T
ABLE
4.
C
ONFIGURATION
R
EGISTER
2 – A
DDRESS
202H
BITS
FUNCTION
DESCRIPTION
0
Cascade Mode
0: First Device
1: Cascaded Device
11-1
Reserved
Must be set to “0”
T
ABLE
5.
C
ONFIGURATION
R
EGISTER
3 – A
DDRESS
203H
BITS
FUNCTION
DESCRIPTION
11-0
Line Buffer Length
See Line Buffer Description Section
T
ABLE
2.
C
ONFIGURATION
R
EGISTER
0 – A
DDRESS
200H
BITS
FUNCTION
DESCRIPTION
0
Line Buffer Mode
0: Delay Mode
1: Recirculate Mode
1
Line Buffer Load
0: Normal Load
1: Parallel Load
2
Odd and Even Field
0: VB Port Disabled
Filtering Port Enable
1: VB Port Enabled
3
Odd and Even Field
0: VB Line Buffer Disabled
Filtering Line Buffer Enable
1: VB Line Buffer Enabled
11-4
Reserved
Must be set to “0”
T
ABLE
3.
C
ONFIGURATION
R
EGISTER
1 – A
DDRESS
201H
F
IGURE
4. RSL C
IRCUITRY
R
R
32
L
L
32
4
RSL
3-0
RND
LIMIT
32
16
16
RSL CIRCUITRY
DATA IN
32
DATA OUT
S
S
5
SELECT
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