參數(shù)資料
型號(hào)： LF2249QC25
廠商： LOGIC DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理外設(shè)
英文描述： 12 x 12-bit Digital Mixer
中文描述： 12-BIT, DSP-MIXER, PQFP120
封裝： PLASTIC, QFP-120
文件頁(yè)數(shù)： 2/8頁(yè)
文件大?。?/td> 70K
代理商： LF2249QC25
DEVICES INCORPORATED
LF2249
12 x 12-bit Digital Mixer
Video Imaging Products
08/16/2000–LDS.2249-J
2
synchronous operation between the
incoming data and all available
control functions. The LF2249 oper-
ates at a clock rate of 40 MHz over the
full commercial temperature and
supply voltage ranges.
Because of its flexibility, the LF2249 is
ideally suited for applications such as
image switching and mixing, digital
quadrature mixing and modulating,
FIR filtering, and arithmetic function
and waveform synthesis.
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all en-
abled registers. All timing specifica-
tions are referenced to the rising edge of
CLK.
Inputs
A
11-0
–D
11-0
— Data Inputs
A
11-0
–D
11-0
are 12-bit data input regis-
ters. Data is latched into the input reg-
isters on the rising edge of CLK. The
contents of the input registers are
clocked into the top of the correspond-
ing 16-stage pipeline delay (pushing the
contents of the register stack down one
register position) on the next clock cycle
if the pipeline register stack is enabled.
The LSBs are A
0
-D
0
(Figure 1a).
CAS
15-0
— Cascade Data Input
CAS
15-0
is the 16-bit cascade data input
port. Data is latched into the register on
the rising edge of CLK. The LSB is CAS
0
(Figure 1a).
ADEL
3-0
A
11-0
ENA
16 : 1
4
12
12
CLK
R
1
R
2
R
16
D
ETAILED
V
IEW
OF
B
LOCK
D
IAGRAM
O
UTLINED
A
REA
10
2
10
2
9
9
8
2
8
11
–2
11
(Sign)
7
2
7
6
2
6
5
2
5
4
2
4
3
2
3
2
2
2
1
2
1
0
2
0
15 14 13
–2
23
2
22
2
21
(Sign)
10
2
18
2
17
2
16
9
8
12 11
2
20
2
19
7
6
5
4
3
2
1
0
2
8
2
15
2
14
2
13
2
12
2
11
2
10
2
9
F
IGURE
1
A
.
I
NPUT
F
ORMATS
15 14 13
–2
23
2
22
2
21
(Sign)
10
2
18
2
17
2
16
9
8
12 11
2
20
2
19
7
6
5
4
3
2
1
0
2
8
2
15
2
14
2
13
2
12
2
11
2
10
2
9
15 14 13
2
15
2
14
2
13
10
2
10
2
9
9
8
2
8
12 11
2
12
2
11
7
2
7
6
2
6
5
2
5
4
2
4
3
2
3
2
2
2
1
2
1
0
2
0
F
IGURE
1
B
.
O
UTPUT
F
ORMATS
Cascade Input
Data Input
Sum Output (Upper 16 bits)
Sum Output (Lower 16 bits)
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