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參數(shù)資料
| 型號： | LF2249 |
| 廠商： | Logic Devices Incorporated |
| 英文描述： | 12 x 12-bit Digital Mixer |
| 中文描述： | 12 × 12位數(shù)字調音臺 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 70K |
| 代理商： | LF2249 |
DEVICES INCORPORATED
LF2249
12 x 12-bit Digital Mixer
Video Imaging Products
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08/16/2000–LDS.2249-J
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ACC — Accumulator Control
The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. When ACC is
HIGH, the emerging products are
added to the sum of the previous prod-
ucts.
RND — Rounding Control
When RND is HIGH, the sum of the
products of the data being input on
the current clock cycle will be
rounded to 16 bits. To avoid the accu-
mulation of roundoff errors, round-
ing is only performed during the first
cycle of each accumulation process.
SWAP — Output Select
The SWAP control allows the user to
access all 24 bits of the accumulator
output by switching between upper
and lower 16-bit words. When SWAP
is HIGH, the upper 16 bits of the accu-
mulator are always output. When
SWAP is LOW, the lower 16 bits of the
accumulator are output on every
other clock cycle. As long as SWAP
remains LOW, new output data will
not be clocked into the output regis-
ters.
OE — Output Enable
When the OE signal is LOW, the
current data in the output registers
is available on the S
15-0
pins. When
OE is HIGH, the outputs are in a
high-impedance state.
Outputs
S
15-0
— Data Output
The current 16-bit result is available
on the S
15-0
outputs. The output data
may be either the upper or lower 16
bits of the accumulator output, de-
pending on the state of SWAP. The
LSB is S
0
(Figure 1b).
Controls
ENA–END — Pipeline Register Enable
Input data in the
N
(
N
= A, B, C, or D)
input register is latched into the corre-
sponding pipeline register stack on
each rising edge of CLK for which EN
N
is LOW. Data already in the
N
register
stack is pushed down one register posi-
tion. When EN
N
is HIGH, the data in
the
N
pipeline register stack does not
change, and the data in the
N
input
register will not be stored in the register
stack.
ADEL
3-0
–DDEL
3-0
— Pipeline Delay
Select
N
DEL (
N
= A, B, C, or D) is the 4-bit
registered pipeline delay select word.
N
DEL determines which stage of the
N
pipeline register stack is routed to the
multiplier inputs. The minimum delay
is one clock cycle (
N
DEL = 0000), and
the maximum delay is 16 clock cycle
(
N
DEL = 1111). Upon power up, the
values of ADEL–DDEL and the con-
tents of the pipeline register stacks are
unknown and must be initialized by the
user.
NEG
1
–NEG
2
— Negate Control
The NEG
1
and NEG
2
controls deter-
mine whether a subtraction or accumu-
lation of products is performed. When
NEG
1
is HIGH, the product
A x B
is
negated, causing the product to be sub-
tracted from the accumulator contents.
Likewise, when NEG
2
is HIGH, the
product
C x D
is negated, causing the
product to be subtracted as well. NEG
1
and NEG
2
determine the operation to
be performed on the data input during
the current clock cycle when ADEL–
DDEL = 0000.
CASEN — Cascade Enable
When CASEN is LOW, data being in-
put on the CAS
15-0
inputs during that
clock cycle will be registered and accu-
mulated internally. When CASEN is
HIGH, the CAS
15-0
inputs are ignored.
FT — Feedthrough Control
When FT is LOW and ADEL–DDEL =
0000, data being input on the CAS
15-0
inputs is delayed three clock cycles to
align the data with the data being input
on the A
11-0
–D
11-0
inputs. When FT is
HIGH, the cascade data being input is
routed around the three delay registers
to simplify the cascading of multiple
devices.
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