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參數(shù)資料
| 型號： | LF2246 |
| 廠商： | Logic Devices Incorporated |
| 英文描述： | 11 x 10-bit Image Filter |
| 中文描述： | 11 × 10位的圖像過濾器 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 248K |
| 代理商： | LF2246 |
DEVICES INCORPORATED
LF2246
11 x 10-bit Image Filter
Video Imaging Products
2-12
08/16/2000–LDS.2246-K
F
IGURE
1
A
.
I
NPUT
F
ORMATS
INPUT REGISTER
HELD
ENB1-4
ENSEL
1
1
Data ‘
N
’
1
0
Coefficient ‘
N
’
0
X
None
X = “Don’t Care”
‘
N
’ = 1, 2, 3, or 4
T
ABLE
1.
I
NPUT
R
EGISTER
C
ONTROL
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all en-
abled registers. All timing specifica-
tions are referenced to the rising edge of
CLK.
Inputs
D1
9–0
–D4
9–0
— Data Input
D1–D4 are 10-bit data input registers.
The LSB is D
N0
(Figure 1a).
C1
10–0
–C4
10–0
— Coefficient Input
C1–C4 are 11-bit coefficient input regis-
ters. The LSB is C
N0
(Figure 1a).
Outputs
S
15–0
— Data Output
The current 16-bit result is available on
the S
15–0
outputs (Figure 1b).
OCEN — Clock Enable
When OCEN is LOW, data in the pre-
mux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register is
held preventing the output register’s
contents from changing (if FSEL does
not change). Accumulation continues
internally as long as ACC is HIGH,
despite the state of OCEN.
FSEL — Format Select
When the FSEL input is LOW, the data
input during the current clock cycle is
assumed to be in fractional two’s
complement format, and the upper 16
bits of the accumulator are presented at
the output. Rounding of the accumula-
tor result to 16 bits is performed if the
accumulator control input ACC is
LOW. When FSEL is HIGH, the data
input is assumed to be in integer two’s
complement format, and the lower 16
bits of the accumulator are presented at
the output. No rounding is performed
when FSEL is HIGH.
ACC — Accumulator Control
The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. If FSEL is also LOW,
one-half LSB rounding to 16 bits is per-
formed on the result. This allows sum-
mations without propagating roundoff
errors. When ACC is HIGH, the emerg-
ing product is added to the sum of the
previous products, without additional
rounding.
F
IGURE
1
B
.
O
UTPUT
F
ORMATS
15 14 13
–2
6
(Sign)
2
5
10
2
1
9
2
0
2
–1
8
12 11
2
3
7
6
5
4
3
2
1
0
2
4
2
2
2
–2
2
–3
2
–4
2
–5
2
–6
2
–7
2
–8
2
–9
Fractional Two’s Complement (FSEL = 0)
15 14 13
–2
15
(Sign)
2
14
2
13
10
2
10
2
9
9
8
2
8
12 11
2
12
2
11
7
2
7
6
2
6
5
2
5
4
2
4
3
2
3
2
2
2
1
2
1
0
2
0
Integer Two’s Complement (FSEL = 1)
Data
9
8
2
8
7
2
7
2
2
2
1
2
1
0
2
0
–2
9
(Sign)
10
–2
10
(Sign)
9
2
9
8
2
8
2
2
2
1
2
1
0
2
0
Integer Two’s Complement (FSEL = 1)
9
8
7
2
1
0
–2
0
(Sign)
2
–1
2
–2
2
–7
2
–8
2
–9
10
–2
1
(Sign)
9
2
0
2
–1
8
2
1
0
2
–7
2
–8
2
–9
Fractional Two’s Complement (FSEL = 0)
Coefficient
Controls
ENB1–ENB4 — Input Enable
The ENB
N
(
N
= 1, 2, 3, or 4) input allows
either or both the D
N
and C
N
registers to
be updated on each clock cycle. When
ENB
N
is LOW, registers D
N
and C
N
are
both strobed by the next rising edge of
CLK. When ENB
N
is HIGH and ENSEL
is LOW, register D
N
is strobed while
register C
N
is held. If both ENB
N
and
ENSEL are HIGH, register D
N
is held,
and register C
N
is strobed (Table 1).
ENSEL — Enable Select
The ENSEL input in conjunction with
the individual input enables ENB1–
ENB4 determines whether the data or
the coefficient input registers will be
held on the next rising edge of CLK
(Table 1).
OEN — Output Enable
When the OEN signal is LOW, the cur-
rent data in the output register is avail-
able on the S
15–0
pins. When OEN is
HIGH, the outputs are in a high-imped-
ance state.
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