
Typical Applications
(Continued)
B. SPEED CONSIDERATIONS
In the system ofFigure 5 with the S/H omitted, if n-bit accu-
racy is desired, the change of the analog input voltage
should be less than
g
1/2 LSB over the A/D conversion
time T
C
. In other words, the analog input slew rate, (rate of
change of input voltage), will cause a slew-induced error
and its magnitude, with respect to the total system error, will
depend on the particular application.
D
V
IN
D
t
max
kg
1/2 LSB
T
C
e
V
FS
2
n
c
T
C
where V
FS
is the full scale voltage of the A/D. Note that
slew induced errors are not affected by the MUX switch time
since we can let the unit settle before starting conversion.
Example: Let T
C
e
40
m
s (MM4357), V
FS
e
10V and n
e
8.
D
V
IN
D
t
à
max
k
1mV
m
s
which is a very small number. A 10 Vp-p sine wave of a
frequency greater than 32 Hz will have higher slew rate
than this. The maximum throughput rate of the above 8-
channel system would be calculated using both the A/D
conversion time and the sum of MUX switch ‘‘ON’’ time
and settling time, i.e.:
Th. R
max
e
1
8(T
C
a
T
MUX
)
e
3k samples/sec/
channel
T
MUX
e
T
ON
a
T
S(ON)
Also notice that Nyquist sampling criteria would allow
each channel to have a signal bandwidth of 1.5 kHz max,
while the slew limit dictates a maximum frequency of 32
Hz. If the input signal has a peak-to-peak voltage less
than 10V, the allowable maximum input frequency can be
calculated by:
f
MAX
e
(Slew Rate)max
q
Vp-p
On the other hand, if the input voltage is not band-limited a
low pass filter with an attenuation of 30 dB or better at 1.5
kHz, should be connected in front of the MUX.
D
t
max
2
n
c
T
A
1. Improving System Speed with a Sample and Hold
The system speed can be improved by using the
S/H shown in Figure 5. This allows a much greater
rate of change of V
IN
.
D
V
IN
k
V
FS
where T
A
is the aperture time of the S/H. This repre-
sents an input slew rate improvement by a factor: T
C
/
T
A
. Here again, the slew rate error is not affected by
the acquisition time of the Sample and Hold since con-
version will start after the S/H has settled. An impor-
tant thing to notice is that the sample and hold errors
will add to the total system error budget; therefore, the
inequality of the
D
V
IN
/
D
t expression should become
more stringent.
Example: T
C
e
40
m
s, T
A
e
0.5
m
s, n
e
8: T
C
/T
A
e
80
So the use of a S/H allows a speed improvement by
nearly two orders of magnitude.
The maximum throughput rate can be calculated by:
1
8(T
A
a
Taq
a
T
C
)
Notice that T
MUX
does not affect the
D
V
IN
/
D
t expression
nor the throughput rate of the system since it may be
switched and settled while the Sample and Hold is in the
Hold mode. This is true, provided that: T
MUX
k
T
A
a
T
C
.
Th. R
max
e
C. SYSTEM EXAMPLE(Figure 7)
The LF398 S/H with a 1000 pF hold capacitor, has an ac-
quisition time of 4
m
s to 0.1% (1/4 LSB error for 8 bits) and
an aperture time of less than 200
m
s. On the other hand,
after the hold command, the output will settle to
g
0.05 mV
in 1
m
s. This, together with the acquisition time, introduces
approximately a
g
1/4 LSB error. Allowing another 1/4 LSB
error for hold step and gain non-linearity, the maximum slew
error (
D
V
IN
/
D
t) should not exceed 1/4 LSB or:
D
V
IN
D
t
(which is the maximum slew rate of a 5 V peak sine wave.
Also notice that, due to the above input slew restrictions,
the analog delay caused by the finite BW of the S/H and the
digital delay caused by the response time of the controller
will be negligible. The maximum throughput rate of the sys-
tem is:
1
8(5
a
40)10
b
6
e
2800 samples/sec/ch.
If the system speed requirements are relaxed, but the A/D
converter is still too slow, then an inexpensive S/H can be
built by using just a capacitor and a low cost FET input op
amp as shown in Figure 8.
s
1
4
c
1
256
c
1
T
A
&
5mV/
m
s
Th. R
max
e
8