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參數(shù)資料
| 型號： | LF13331N |
| 英文描述： | IC-ANALOGUE SWITCH |
| 中文描述： | 集成電路模擬廣播 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 265K |
| 代理商： | LF13331N |
Application Hints
GENERAL INFORMATION
These devices are monolithic quad JFET analog switches
with ‘‘ON’’ resistances which are essentially independent of
analog voltage or analog current. The leakage currents are
typically less than 1 nA at 25
§
C in both the ‘‘OFF’’and ‘‘ON’’
switch states and introduce negligible errors in most appli-
cations. Each switch is controlled by minimum TTL logic
levels at its input and is designed to turn ‘‘OFF’’ faster than
it will turn ‘‘ON.’’ This prevents two analog sources from
being transiently connected together during switching. The
switches were designed for applications which require
break-before-make action, no analog current loss, medium
speed switching times and moderate analog currents.
Because these analog switches are JFET rather than
CMOS, they do not require special handling.
LOGIC INPUTS
The logic input (IN), of each switch, is referenced to two
forward diode drops (1.4V at 25
§
C) from the reference sup-
ply (V
R
) which makes it compatible with DTL, RTL, and TTL
logic families. For normal operation, the logic ‘‘0’’ voltage
can range from 0.8V to
b
4.0V with respect to V
R
and the
logic ‘‘1’’ voltage can range from 2.0V to 6.0V with respect
to V
R
, provided V
IN
is not greater than (V
CC
b
2.5V). If the
input voltage is greater than (V
CC
b
2.5V), the input current
will increase. If the input voltage exceeds 6.0V or
b
4.0V
with respect to V
R
, a resistor in series with the input should
be used to limit the input current to less than 100
m
A.
ANALOG VOLTAGE AND CURRENT
Analog Voltage
Each switch has a constant ‘‘ON’’ resistance (R
ON
) for ana-
log voltages from (V
EE
a
5V) to (V
CC
b
5V). For analog volt-
ages greater than (V
CC
b
5V), the switch will remain ON in-
dependent of the logic input voltage. For analog voltages
less than (V
EE
a
5V), the ON resistance of the switch will
increase. Although the switch will not operate normally
when the analog voltage is out of the previously mentioned
range, the source voltage can go to either (V
EE
a
36V) or
(V
CC
a
6V), whichever is more positive, and can go as nega-
tive as V
EE
without destruction. The drain (D) voltage can
also go to either (V
EE
a
36V) or (V
CC
a
6V), whichever is
more positive, and can go as negative as (V
CC
b
36V) with-
out destruction.
Analog Current
With the source (S) positive with respect to the drain (D), the
R
ON
is constant for low analog currents, but will increase at
higher currents (
l
5 mA) when the FET enters the satura-
tion region. However, if the drain is positive with respect to
the source and a small analog current loss at high analog
currents (Note 6) is tolerable, a low R
ON
can be maintained
for analog currents greater than 5 mA at 25
§
C.
LEAKAGE CURRENTS
The drain and source leakage currents, in both the ON and
the OFF states of each switch, are typically less than 1 nA
at 25
§
C and less than 100 nA at 125
§
C. As shown in the
typical curves, these leakage currents are Dependent on
power supply voltages, analog voltage, analog current and
the source to drain voltage.
DELAY TIMES
The delay time OFF (t
OFF
) is essentially independent of
both the analog voltage and temperature. The delay time
ON (t
ON
) will decrease as either (V
CC
b
V
A
) decreases or
the temperature decreases.
POWER SUPPLIES
The voltage between the positive supply (V
CC
) and either
the negative supply (V
EE
) or the reference supply (V
R
) can
be as much as 36V. To accommodate variations in input
logic reference voltages, V
R
can range from V
EE
to
(V
CC
b
4.5V). Care should be taken to ensure that the power
supply leads for the device never become reversed in polar-
ity or that the device is never inadvertantly installed back-
wards in a test socket. If one of these conditions occurs, the
supplies would zener an internal diode to an unlimited cur-
rent; and result in a destroyed device.
SWITCHING TRANSIENTS
When a switch is turned OFF or ON, transients will appear
at the load due to the internal transient voltage at the gate
of the switch JFET being coupled to the drain and source by
the junction capacitances of the JFET. The magnitude of
these transients is dependent on the load. A lower value R
L
produces a lower transient voltage. A negative transient oc-
curs during the delay time ON, while a positive transient
occurs during the delay time OFF. These transients are rela-
tively small when compared to faster switch families.
DISABLE NODE
This node can be used, as shown inFigure 5, to turn all the
switches in the unit off independent of logic inputs. Normal-
ly, the node floats freely at an internal diode drop (
&
0.7V)
above V
R
. When the external transistor in Figure 5 is satu-
rated, the node is pulled very close to V
R
and the unit is
disabled. Typically, the current from the node will be less
than 1 mA. This feature is not available on the LF11201 or
LF11202 series.
TL/H/5667–6
FIGURE 5. Disable Function
6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LF13331N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPST Analog Switch |
| LF13331N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPST Analog Switch |
| LF13332 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Quad SPST JFET Analog Switches |
| LF13332D | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Quad SPST JFET Analog Switches |
| LF13332M | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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