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參數(shù)資料
| 型號(hào)： | LE28F4001CTS-12 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 4M-Bit (512k 】 8) Flash EEPROM |
| 中文描述： | 4分位（為512k】8）閃存EEPROM |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大小： | 168K |
| 代理商： | LE28F4001CTS-12 |
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LE28F4001CTS-12
4M-Bit
Flash
EEPROM
Preliminary
Specifications
SANYO
Electric
Co.,
Ltd.
5/14
Read_ID Operation
The Read_ID operation is initiated by writing a single
command (90H). A read of address 0000H will outputs the
manufacturer’s code (BFH). A read of address 0001H will outputs
the device code (04H).Any other valid command will terminate this
operation.
Data Protection from Inadvertent Writes
In order to protect the integrity of nonvolatile data storage, the
LE28F4001C provides hardware and software features to prevent
writes to the device, for example, during system power-up or
power-down. Such provisions are described below.
Hardware Write Protection
The LE28F4001C is designed with hardware features to
prevent inadvertent writes. This is done in the following ways:
1. Write Inhibit Mode:
OE
low,
CE
high or
WE
high
inhibit the write operation.
2. Noise and Glitch Protection: Write operations are initiated
when the
WE
pulse width is less than 15 ns.
3. After power-up the device is in the read mode and the
device is in the write protect state.
Software Data Protection
Provisions have been made to further prevent inadvertent writes
through software. In order to perform the write functions of erase
or program, a two-step command sequence consisting of a setup
command followed by an execute command avoids inadvertent
erasing or programming of the device.
The LE28F4001C will default to write protect after power-up.
A sequence of seven consecutive reads at specified device
addresses will unprotect the device. The address sequence is
1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The
address has to be latched in the rising edge of
OE
or
CE
,
whichever occurs first. A similar seven read sequence of 1823H,
1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect the
device. Also, refer to Figure 11, 12 for the 7-read-sequence
Software Write Protection. The DQ pins can be in any state (i.e.,
high, low, or High-Z).
End of Write Detection
Detection of where a write cycle ended is necessary to optimize
system performance. The end of a write cycle (erase or program)
can be detected by three means: 1) monitoring the
DATA
polling
bit; 2) monitoring the Toggle bit; 3) by two successive reads of the
same data. These three detection mechanisms are described below.
DATA
Polling (DQ7)
The LE28F4001C features
DATA
Polling to indicate the and
of a write cycle. During a write cycle, any attempt to read the last
byte loaded will result in the complement of the loaded data on
DQ7. Once the write cycle is completed, DQ7 will show true data.
See Figure 13 for timing waveforms. In order for
DATA
Polling
to function correctly, the byte being polled must be erased prior to
programming.
Toggle Bit (DQ6)
An alternate means for determining the end of a write cycle is
by monitoring the Toggle Bit DQ6. During a write operation,
successive attempts to read data from the device will result in DQ6
toggling between logic "1" (high) and "0" (low). Once the write
cycle has completed, DQ6 will stop toggling and valid data will be
read. The Toggle Bit may be monitored any time during the write
cycle. See Figure 14 for timing waveforms.
Successive Reads
An alternate means for determining the end of a write cycle is
by reading the same address for two consecutive data matches.
Product Identification
The Product Identification mode identifies the device and
manufacturer as SANYO. This mode may be accessed by hardware
or software operations. The hardware operation is typically used by
an external programming to identify the correct algorithm for the
SANYO LE28F4001C. Users may wish to use the software
operation to identify the device (i.e., using the device code). For
details, see Table 2 for the hardware operation. The manufacturer
and device codes are the same for both operations.
Notes for Operation
During power up, the device’s state should be the write
inhibition mode. (During power up, the device’s state should be
CE
=V
IH
or
OE
=V
IL
or
WE
=V
IH
)
If
CE
=
WE
=V
IL
and
OE
=V
IH
during power up, RESET
command should be asserted before operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LE28F4001M | 4 MEG (524288 words x 8 bits) Flash Memory |
| LE28F4001M-15 | |
| LE28F4001T-15 | |
| LE28FV4001CTS-20 | 4M-Bit Flash EEPROM |
| LE28FV4001T | 4MEG (52488 x 8 Bits) Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LE28F4001CTS-12M01-E | 制造商:ON Semiconductor 功能描述:P-FLASH MEMORY(8M) - Trays |
| LE28F4001CTS12-MPB-E | 制造商:ON Semiconductor 功能描述:P-FLASH MEMORY(8M) - Trays |
| LE28F4001M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4 MEG (524288 words x 8 bits) Flash Memory |
| LE28F4001M-15 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述: |
| LE28F4001M-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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