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參數(shù)資料
| 型號(hào)： | LC89975M |
| 廠(chǎng)商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | PAL-Format Delay Line |
| 中文描述： | PAL制式格式延遲線(xiàn) |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | LC89975M |
Chrominance System Characteristics (with no signal applied to the Y-IN pin)
Luminance System Characteristics (with no signals applied to the C-IN1 and C-IN2 pins)
No. 5391-4/7
LC89975M
Parameter
Symbol
Test conditions
Switch states
min
typ
max
Unit
SW1
SW2
SW3
Pin voltage (input)
V
INC-1
V
INC-2
V
OUTC-1
V
OUTC-2
G
VC-1
G
VC-2
C
D-1
C
D-2
L
NC-1
L
NC-2
L
CK3C-1
L
CK3C-2
L
CK1C-1
L
CK1C-2
N
C-1
N
C-2
Z
OC-1
Z
OC-2
T
DC-1
T
DC-2
a
a
b
2.2
2.7
3.2
V
2
b
a
b
Pin voltage (output)
a
a
b
1.5
2.0
2.5
V
b
a
b
Voltage gain
3
a
a
b
0
2
4
dB
b
a
b
Comb depth
4
a
a
b
—
–40
–35
dB
b
a
b
Linearity
5
a
a
b
–0.3
0.0
+0.3
dB
b
a
b
Clock leakage (3·fsc)
a
a
b
—
10
50
mVrms
6
b
a
b
Clock leakage fsc)
a
a
b
—
0.5
1.5
mVrms
b
a
b
Noise
7
a
a
b
—
0.5
2.0
mVrms
b
a
b
Output impedance
8
a
a
a, b
200
350
500
b
a
a, b
0H delay time
9
a
a
b
—
245
—
ns
b
a
b
Parameter
Symbol
Test conditions
Switch states
min
typ
max
Unit
SW1
SW2
SW3
Pin voltage (input)
V
INY-1
V
INY-2
V
OUTY-1
V
OUTY-2
G
VY-1
G
VY-2
G
FY-1
G
FY-2
D
GY-1
D
GY-2
D
PY-1
D
PY-2
L
SY-1
L
SY-2
L
CK3Y-1
L
CK3Y-2
L
CK1Y-1
L
CK1Y-2
N
Y-1
N
Y-2
Z
OY-1
Z
OY-2
T
DY-1
T
DY-2
a
a
b
1.7
2.2
2.7
V
10
b
a
b
Pin voltage (output)
a
a
b
0.8
1.3
1.8
V
b
a
b
Voltage gain
11
a
a
b
0
2
4
dB
b
a
b
Frequency response
12
a
b
b
–2
0
2
dB
b
b
b
Differential gain
a
a
b
0
5
7
%
13
b
a
b
Differential phase
a
a
b
0
5
7
deg
b
a
b
Linearity
14
a
a
b
37
40
43
%
b
a
b
Clock leakage (3·fsc)
a
a
b
—
10
50
mVrms
15
b
a
b
Clock leakage (fsc)
a
a
b
—
0.5
1.5
mVrms
b
a
b
Noise
16
a
a
b
—
0.5
2.0
mVrms
b
a
b
Output impedance
17
a
a
c, b
250
400
550
b
a
c, b
Delay time
18
a
a
b
—
63.88
—
μs
b
a
b
—
63.43
—
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